Pulse-drive resonant clock with on-the-fly mode change

Patent metadata

Field	Value
Publication number	US-9612614-B2
Application number	US-201514814780-A
Country	US
Kind code	B2
Filing date	Jul 31, 2015
Priority date	Jul 31, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A pulse-drive resonant clock with on-the fly mode changing provides robust operation in a resonant clock distribution network, in particular for processor circuits having a dynamically-varied operating frequency. The clock drivers for the resonant clock distribution network include a pulse width control circuit having selectable operating modes corresponding to multiple clocking modes of the resonant clock distribution network. The pulse width control circuit includes a delay line that has a selectable delay length to provide pulse enable signals that control the pulse widths of the clock drivers in a sector of the resonant clock distribution network. The delay line responds to a mode control signal so that at least one pulse width of the output is changed from a first pulse width to a second pulse width without generating half-cycles with a pulse width narrower than the first or second pulse width.

First claim

What is claimed is:

1. A clock driver circuit for a resonant clock distribution network, the clock driver circuit comprising:
at least one clock driver output stage having an output for driving a drive point of a sector of the resonant clock distribution network, having a clock input coupled to a global clock signal, and having a first enable input for enabling and disabling a pull-up driver of the at least one clock driver output stage and a second enable input for enabling and disabling a pull-down driver of the at least one clock driver output stage;
a delay line having a selectable delay selected in conformity with a mode select input and further having an input for receiving the global clock signal, wherein the delay line further includes a mode select control logic responsive to the mode select input; and
a clock pulse width control logic having a first output coupled to the first enable input of the clock driver output stage, a second output coupled to the second enable input of the clock driver output stage and an input coupled to an output of the delay line, wherein the clock pulse width control logic enables the at least one clock driver output stage in response to changes in state of global clock signal and disables the at least one clock driver output stage when the changes in state of the global clock signal have propagated through the delay line, and wherein the mode select control logic prevents the clock pulse width control logic from enabling the at least one clock driver output stage for a duration shorter than a delay time of the delay line when the mode select input changes state.

2. The clock driver circuit of claim 1 , wherein the delay line comprises:
a plurality of inverters connected in cascade; and
a multiplexer having a plurality of inputs coupled to at least some corresponding ones of the plurality of inverters and an output coupled to the first and second inputs of the clock pulse width control logic, wherein the mode select control logic has an input coupled to the mode select input and an output coupled to the select input of the multiplexer for delaying a state change of the select input of the multiplexer until a predetermined time after a last transition of the global clock signal has occurred.

3. The clock driver circuit of claim 2 , wherein the mode select control logic comprises:
a second delay line having an input coupled to the global clock signal; and
a latch having an input coupled to the global clock signal, a clock input coupled to an output of the second delay line and an output coupled to the mode select input.

4. The clock driver circuit of claim 1 , wherein the delay line comprises:
a first plurality of inverters connected in cascade;
a first multiplexer having a plurality of inputs coupled to at least some corresponding ones of the first plurality of inverters and an output coupled to the first input of the clock pulse width control logic;
a second plurality of inverters connected in cascade; and
a second multiplexer having a plurality of inputs coupled to at least some corresponding ones of the second plurality of inverters and an output coupled to the second input of the clock pulse width control logic, and wherein the mode select control logic has an input coupled to the mode select input and an output coupled to the select inputs of the first multiplexer and the second multiplexer for delaying a state change of the select inputs of the first multiplexer and the second multiplexer until a predetermined time after a last corresponding transition of the global clock signal has occurred.

5. The clock driver circuit of claim 4 , wherein the mode select control logic comprises:
a second delay line having an input coupled to the global clock signal;
a latch having an input coupled to the global clock signal, a clock input coupled to an output of the second delay line and an output coupled to the select input of the first multiplexer;
a third delay line having an input coupled to the global clock signal;
a second latch having an input coupled to the global clock signal, a clock input coupled to an output of the third delay line and an output coupled to the select input of the second multiplexer.

6. A resonant clock distribution network, comprising:
a conductive grid;
a plurality of clock driver output stages having outputs for driving drive points of the grid, wherein the clock driver output stages have a clock input coupled to a global clock signal, a first enable input for enabling and disabling a pull-up driver of the clock driver output stage and a second enable input for enabling and disabling a pull-down driver of the clock driver output stage;
a delay line having a selectable delay selected in conformity with a mode select input and further having an input for receiving the global clock signal, wherein the delay line further includes a mode select control logic responsive to the mode select input; and
a clock pulse width control logic having a first output coupled to the first enable input of the clock driver output stages, a second output coupled to the second enable input of the clock driver output stages and an input coupled to an output of the delay line, wherein the clock pulse width control logic enables the clock driver output stages in response to changes in state of global clock signal and disables the clock driver output stages when the changes in state of the global clock signal have propagated through the delay line, and wherein the mode select control logic prevents the clock pulse width control logic from enabling the clock driver output stages for a duration shorter than a delay time of the delay line when the mode select input changes state.

7. The resonant clock distribution network of claim 6 , wherein the delay line comprises:
a plurality of inverters connected in cascade; and
a multiplexer having a plurality of inputs coupled to at least some corresponding ones of the plurality of inverters and an output coupled to the first and second inputs of the clock pulse width control logic, wherein the mode select control logic has an input coupled to the mode select input and an output coupled to the select input of the multiplexer for delaying a state change of the select input of the multiplexer until a predetermined time after a last transition of the global clock signal has occurred.

8. The resonant clock distribution network of claim 7 , wherein the mode select control logic comprises:
a second delay line having an input coupled to the global clock signal; and
a latch having an input coupled to the global clock signal, a clock input coupled to an output of the second delay line and an output coupled to the mode select input.

9. The resonant clock distribution network of claim 6 , wherein the delay line comprises:
a first plurality of inverters connected in cascade;
a first multiplexer having a plurality of inputs coupled to at least some corresponding ones of the first plurality of inverters and an output coupled to the first input of the clock pulse width control logic;
a second plurality of inverters connected in cascade;
a second multiplexer having a plurality of inputs coupled to at least some corresponding ones of the second plurality of inverters and an output coupled to the second input of the clock pulse width control logic and wherein the mode select control logic has an input coupled to the mode select input and an output coupled to the select inputs of the first multiplexer and the second multiplexer for delaying a state change of the select inputs of the first multiplexer and the second multiplexer until a predetermined time after a last corresponding transition of the global clock signal has occurred.

10. A cl

Assignees

• IBM

Inventors

• Bucelot Thomas J
• Franch Robert L
• Restle Phillip J
• Shan David Wen-Hao
• Vezyrtzis Christos

Classifications

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K5/159

  Applications of delay lines not covered by the preceding subgroups · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title