Interconnect structure configured to control solder flow and method of manufacturing of same

Patent metadata

Field	Value
Publication number	US-9609752-B1
Application number	US-201414213833-A
Country	US
Kind code	B1
Filing date	Mar 14, 2014
Priority date	Mar 15, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

An interconnect structure and method for manufacturing the same includes a substrate and a copper trace line defined on a surface of the substrate. The copper trace line includes a transmission line and a contact pad. The copper trace line is plated with a layer of metal which will oxidize if exposed to the atmosphere. The layer of metal is further plated with a layer of gold. The gold layer is selectively applied to the transmission line and the contact pad to define a gap on the transmission line at the contact pad. The metal layer is exposed in the gap. An oxide layer is formed on the metal layer in the gap. The oxide layer and the substrate surround the contact pad define a barrier to spread of solder.

First claim

What is claimed is:

1. An interconnect structure configured to control solder flow, comprising:
a dielectric substrate;
a copper trace defined on a surface of said substrate, the copper trace defining at least a contact pad and a transmission line in contact with the contact pad;
a metal layer covering said copper trace; and
a gold layer covering the metal layer on the contact pad and transmission line, the gold layer defining a gap over a portion of the transmission line adjacent or near the contact pad, the metal layer exposed in the gap, an oxide being on the exposed metal layer.

2. The interconnect structure of claim 1 , said gold layer having a thickness sufficient to cause a radio frequency (RF) signal transmitted on said transmission line to propagate substantially within said gold layer.

3. The interconnect structure of claim 2 , wherein said gold layer has a thickness of about 30 microinches to about 40 microinches.

4. The interconnect structure of claim 1 , wherein said metal layer comprises nickel.

5. The interconnect structure of claim 1 , wherein said metal layer has a minimum thickness of about 40 microinches.

6. The interconnect structure of claim 1 , said metal layer having a thickness sufficient to minimize diffusion from said gold layer into said copper trace.

7. The interconnect structure of claim 1 , wherein said gold layer covers said copper trace along an entire length of said transmission line, except at a location defined by said gap.

8. The interconnect structure of claim 1 , wherein said gap has a dimension along the longitudinal extent of said transmission line of about 25 microns to about 100 microns.

9. The interconnect structure of claim 1 , wherein said contact pad has a dimension about its length of about 50 microns to about 200 microns.

10. A method of manufacturing an interconnect structure controlling solder flow, said method comprising the steps of:
forming, on a copper clad board substrate, a metal layer defining a circuit trace including at least a contact pad and a transmission line in contact with the contact pad;
forming a gold layer over portions of said metal layer to define a gap exposing the metal layer at a portion of the transmission line adjacent to or near the contact pad; and
forming an oxide layer on a surface of the metal layer at a location of the gap.

11. The method of claim 10 , wherein the forming an oxide layer on the metal layer comprises subjecting the exposed metal layer portions to an environment having a temperature elevated above room temperature.

12. The method of claim 10 , further comprising:
etching said interconnect structure to remove copper cladding on the substrate at areas not covered by the metal layer to define at least one circuit trace.

13. The method of claim 10 , wherein the metal layer is formed to a thickness of about 40 microinches.

14. The method of claim 10 , wherein the gold layer is formed to a thickness of about 30 microinches to about 40 microinches.

15. The method of claim 10 , wherein the gap is defined to have a dimension along the longitudinal extent of the transmission line of about 25 microns to about 100 microns.

16. The method of claim 10 , wherein the metal layer comprises nickel.

17. The method of claim 10 , wherein the metal layer is formed using a nickel/gold electroplating process.

18. The method of claim 10 , wherein said gold layer is formed using a gold electro-plating technique to a thickness of at least about 30 microinches.

19. An integrated circuit flip chip assembly for controlling solder flow comprising:
an integrated circuit chip having a first surface, said first surface having at least one first contact pad, each of said at least one first contact pad having a solder ball defined thereon; and
an interconnect structure for receiving said integrated circuit chip, said interconnect structure comprising:
a dielectric substrate;
at least one copper trace defined on a surface of said substrate, said copper trace defining a transmission line and a second contact pad configured to bond via said solder ball to said at least one first contact pad;
a metal layer selectively disposed on said at least one copper trace, said metal layer covering said transmission line and said second contact pad;
a gold layer selectively disposed on said metal layer at locations of the second contact pad and a portion of said transmission line, said gold layer defining a gap adjacent to or near said second contact pad, a surface of said metal layer being exposed in the gap; and
an oxide layer on the exposed surface of said metal layer at said gap.

20. The integrated circuit flip chip assembly of claim 19 , wherein said metal layer comprises nickel.

Assignees

• Lockheed Corp

Inventors

• Blass Daniel L
• Ajoian Jack V

Classifications

• H10W72/00 Primary

  Interconnections or connectors in packages · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title