Compact row decoder with multiple voltage support

US9609254B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9609254-B2
Application numberUS-201414538772-A
CountryUS
Kind codeB2
Filing dateNov 11, 2014
Priority dateDec 29, 2013
Publication dateMar 28, 2017
Grant dateMar 28, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

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The present invention provides a compact row decoder with multiple voltage support. The row decoder may include a global driver and a plurality of row-level drivers. The global driver may include one or more voltage level shifters that are operable to provide multiple voltages required to drive each of the plurality of row-level drivers. The plurality of row-level drivers each may include only one voltage level shifter. In an example, the row-level driver includes an address decoder implemented in a digital domain providing an address selection signal, a voltage level shifter to convert the address selection signal to an analog domain, and a row driver receiving driving signals from the global driver. The row driver has no voltage level shifter contained therein. Thus, the row-level drivers and the row decoder may be very compact. The present invention further provides a CMOS image sensor including the row decoder and a method of operating the CMOS image sensor.

First claim

Opening claim text (preview).

The invention claimed is: 1. A row decoder, comprising: a plurality of row-level drivers configured to drive a plurality of rows of pixels; and a global driver comprising at least one global voltage level shifter that is operable to drive the plurality of row-level drivers; wherein each of the plurality of row-level drivers comprises an address decoder implemented in a digital domain, a row driver implemented in an analog domain, and only one row-level voltage level shifter connected between the address decoder and the row driver, and wherein said row driver has no voltage level shifter included therein. 2. The row decoder according to claim 1 , wherein the at least one global voltage level shifter is configured to provide driving signals in an analog domain to the row driver. 3. The row decoder according to claim 1 , wherein the row-level voltage level shifter is configured to convert a row access signal from a digital domain to an analog domain. 4. The row decoder according to claim 1 , wherein the at least one global voltage level shifter further comprises: a first global voltage level shifter configured to convert a reset control signal from a digital domain to an analog domain; a second global voltage level shifter configured to convert a transfer control signal from the digital domain to the analog domain; and a third global voltage level shifter configured to convert a row selection control signal from the digital domain to the analog domain, wherein the reset control signal, the transfer control signal and the row selection control signal in the analog domain are provided to the row driver. 5. The row decoder according to claim 4 , wherein the row driver comprises: a reset channel configured to receive the reset control signal and generate a reset signal for a reset operation of a pixel; a transfer channel configured to receive the transfer control signal and generate a transfer signal for a charge transfer operation of a pixel; and a read channel configured to receive the row selection control signal and generate a row selection signal for a read operation of a pixel. 6. A CMOS image sensor, comprising a plurality of rows of pixels; and a row decoder, wherein the row decoder comprises a plurality of row-level drivers configured to drive the plurality of rows of pixels; and a global driver comprising at least one global voltage level shifter that is operable to drive the plurality of row-level drivers; wherein each of the plurality of row-level drivers comprises an address decoder implemented in a digital domain, a row driver implemented in an analog domain, and only one row-level voltage level shifter connected between the address decoder and the row driver; and wherein said row driver has no voltage level shifter included therein. 7. A method for operating a CMOS image sensor of claim 6 comprising: generating, by the global driver, voltages in an analog domain required for operation of the row-level drivers; and providing the voltages in the analog domain from the global driver to the row-level drivers. 8. The method according to claim 7 , wherein the step of providing the voltages comprises providing the voltages in the analog domain to the row driver. 9. The method according to claim 8 , wherein the step of generating the voltages comprises converting, by at least one voltage level shifter included in the global driver, the voltages from the digital domain to the analog domain. 10. The method according to claim 8 , further comprising: generating, by the address decoder, a row access signal in the digital domain; and converting, by the row-level voltage level shifter connected between the address decoder and the row driver, the row access signal from the digital domain to the analog domain. 11. The method according to claim 8 , wherein the plurality of row-level drivers each comprise only one voltage level shifter.

Assignees

Inventors

Classifications

  • G11C8/10Primary

    Decoders · CPC title

  • Circuitry for scanning or addressing the pixel array · CPC title

  • H04N5/376Primary

    Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US9609254B2 cover?
The present invention provides a compact row decoder with multiple voltage support. The row decoder may include a global driver and a plurality of row-level drivers. The global driver may include one or more voltage level shifters that are operable to provide multiple voltages required to drive each of the plurality of row-level drivers. The plurality of row-level drivers each may include only …
Who is the assignee on this patent?
Guo Li, Zhang Guangbin, Cista Sys Corp
What technology area does this patent fall under?
Primary CPC classification G11C8/10. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).