Solid-state imaging device, drive method thereof and camera system

Patent metadata

Field	Value
Publication number	US-9609187-B2
Application number	US-201514690952-A
Country	US
Kind code	B2
Filing date	Apr 20, 2015
Priority date	Apr 28, 2010
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A solid-state imaging device includes: pixel signal reading lines; a pixel unit in which pixels including photoelectric conversion elements are arranged; and a pixel signal reading unit performing reading of pixel signals from the pixel unit through the pixel signal reading lines, wherein the pixel signal reading unit includes current source circuits each of which includes a load element as a current source connected to the pixel signal reading line forming a source follower, and the current source circuit includes a circuit generating electric current according to a slew rate of the pixel signal reading line and replicating electric current corresponding to the above electric current to flow in the current source.

First claim

What is claimed is:

1. A solid-state imaging device comprising:
a transfer transistor configured to disconnect a photoelectric conversion element from a gate of an amplifier transistor and to electrically connect the photoelectric conversion element directly to the gate of the amplifier transistor;
a selection transistor configured to disconnect a drain of a load transistor from a source/drain region of the amplifier transistor and to electrically connect the drain of the load transistor directly to the source/drain region of the amplifier transistor;
a gate of a first transistor electrically connected directly to a gate of the load transistor and a drain of the first transistor; and
a drain of a replica circuit transistor directly electrically connected to the gate of the first transistor.

2. The solid-state imaging device according to claim 1 , further comprising:
a reset transistor that is controllable to disconnect a power supply line from the gate of the amplifier transistor and to electrically connect the power supply line directly to the gate of the amplifier transistor.

3. The solid-state imaging device according to claim 1 , wherein the first transistor and the load transistor are of a same conductive type.

4. The solid-state imaging device according to claim 1 , wherein the load transistor is an NMOS transistor.

5. The solid-state imaging device according to claim 1 , further comprising:
a source of the load transistor directly electrically connected to a source of the first transistor.

6. The solid-state imaging device according to claim 1 , wherein the first transistor is an NMOS transistor and the replica circuit transistor is a PMOS transistor.

7. The solid-state imaging device according to claim 1 , wherein the first transistor is of a first conductive type and the replica circuit transistor is of a second conductive type.

8. The solid-state imaging device according to claim 1 , wherein the first transistor of a conductive type that is opposite to the replica circuit transistor.

9. The solid-state imaging device according to claim 1 , further comprising:
a current source directly electrically connected to the source of the replica circuit transistor.

10. The solid-state imaging device according to claim 1 , further comprising:
a gate of the replica circuit transistor directly electrically connected to the drain of the load transistor.

11. The solid-state imaging device according to claim 1 , further comprising:
an electrode of a capacitor directly electrically connected to a source of the replica circuit transistor.

12. The solid-state imaging device according to claim 11 , further comprising:
another electrode of the capacitor directly electrically connected to a reference potential.

13. The solid-state imaging device according to claim 12 , wherein the source of the load transistor and the source of the first transistor are electrically connected directly to the reference potential.

14. The solid-state imaging device according to claim 1 , further comprising:
a gate of the replica circuit transistor directly electrically connected to a source of a second transistor and to a drain of a third transistor.

15. The solid-state imaging device according to claim 14 , wherein the first transistor and the second transistor are of a same conductive type.

16. The solid-state imaging device according to claim 14 , wherein the first transistor and the third transistor are of a same conductive type.

17. The solid-state imaging device according to claim 14 , wherein the second transistor and the third transistor are of a same conductive type.

18. The solid-state imaging device according to claim 14 , further comprising:
a gate of the second transistor directly electrically connected to the vertical signal line.

19. The solid-state imaging device according to claim 14 , further comprising:
a source of the third transistor directly electrically connected to the source of the first transistor.

20. The solid-state imaging device according to claim 14 , further comprising:
a gate of the third transistor directly electrically connected to a bias power supply.

21. A camera system comprising:
the solid-state imaging device according to claim 1 ;
an optical system configured to direct incident light onto the solid-state imaging device.

Assignees

• Sony Corp

Inventors

• Gendai Yuji
• Toyomura Junji
• Kanagawa Norifumi

Classifications

• H04N25/00 Primary

  Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title

• H04N23/54 Primary

  Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N5/378

  Electricity · mapped topic

• H04N5/335

  Electricity · mapped topic