Systems and methods for synchronization of clock signals

US9608754B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9608754-B2
Application numberUS-201514639896-A
CountryUS
Kind codeB2
Filing dateMar 5, 2015
Priority dateSep 22, 2011
Publication dateMar 28, 2017
Grant dateMar 28, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A system may include a transmitting device. The transmitting device may include one or more terminals for receiving a data signal and a first clock signal. A first phase lock loop may lock a phase of an initial periodic signal with a phase of the first clock signal, the first phase lock loop including a divider to generate the initial periodic signal based on the first clock signal. A decimation module may sample the initial periodic signal at a decimated rate of a backplane clock, the backplane clock being asynchronous with a clock that generated the first clock signal. A transmitting data block interface may construct data blocks and provide the data blocks to a receiving device, each of one or more of the data blocks including a portion of the data signal and at least one sample of the initial periodic signal.

First claim

Opening claim text (preview).

The invention claimed is: 1. A system for clock signaling, the system comprising: a transmitting device including: one or more terminals configured to receive a data signal and a first clock signal; a first phase lock loop configured to lock a phase of an initial periodic signal with a phase of the first clock signal, the first phase lock loop including a divider to generate the initial periodic signal based on the first clock signal; decimation circuitry configured to sample the initial periodic signal at a decimated rate of a backplane clock, the backplane clock being asynchronous with a clock that generated the first clock signal; and a transmitting data block interface configured to construct data blocks and provide the data blocks to a receiving device, each of one or more of the data blocks including a portion of the data signal and at least one sample of the initial periodic signal. 2. The system of claim 1 , wherein the transmitting data block interface is further configured to construct the data blocks to include data from the one or more terminals. 3. The system of claim 2 , wherein the receiving device includes: a receiving data block interface configured to receive the data blocks; a second phase lock loop configured to lock a phase of the at least one sample of the initial periodic signal with a phase of a second clock signal to produce a phase locked signal; and a clock signal generator configured to recreate the first clock signal as a recreated clock signal based at least in part on the phase locked signal. 4. The system of claim 3 , wherein the receiving device includes timing circuitry coupled to the clock signal generator, the timing circuitry being configured to provide the recreated clock signal to one or more of an Outdoor Unit (“ODU”) and customer equipment coupled to the receiving device. 5. The system of claim 3 , wherein the receiving data block interface operates based on a first backplane data clock. 6. The system of claim 5 , wherein the receiving data block interface operates based on a second clock signal that is not the first clock signal. 7. The system of claim 3 , wherein the second phase lock loop further comprises second decimation circuitry configured to generate a subset of samples of the recreated clock signal to provide feedback and assist in locking a phase of the recreated clock signal with the phase of the at least one sample of the initial periodic signal. 8. The system of claim 1 , wherein the transmitting data block interface comprises a Time Division Multiplexing (“TDM”) interface. 9. The system of claim 8 , wherein the data blocks comprise a plurality of TDM frames. 10. The system of claim 9 , wherein the transmitting data block interface incorporates a plurality of bits based on the at least one sample of the initial periodic signal in each TDM frame. 11. A method comprising: receiving a data signal; receiving a first clock signal; generating an initial periodic signal based on the first clock signal; locking a phase of the initial periodic signal with a phase of the first clock signal; sampling the initial periodic signal at a decimated rate of a backplane clock, the backplane clock being asynchronous with a clock that generated the first clock signal; constructing data blocks, each of one or more of the data blocks including a portion of the data signal and at least one sample of the initial periodic signal; and providing the data blocks to a receiving device. 12. The method of claim 11 , further comprising constructing the data blocks to include data from one or more terminals. 13. The method of claim 11 , further comprising: receiving the data blocks; locking a phase of the at least one sample of the initial periodic signal with a phase of a second clock signal to produce a phase locked signal; and recreating the first clock signal as a recreated clock signal based at least in part on the phase locked signal. 14. The method of claim 13 , further comprising providing the recreated clock signal to one or more of an Outdoor Unit (“ODU”) and customer equipment coupled to the receiving device. 15. The method of claim 13 , wherein constructing the data blocks comprises Time Division Multiplexing (“TDM”) the data blocks. 16. The method of claim 15 , wherein the data blocks comprise a plurality of TDM frames. 17. The method of claim 16 , wherein constructing the data blocks comprises incorporating a plurality of bits based on the at least one sample of the initial periodic signal in each TDM frame. 18. A system comprising: means for receiving a data signal and for receiving a first clock signal; means for generating an initial periodic signal based on the first clock signal and for locking a phase of the initial periodic signal with a phase of the first clock signal; means for sampling the initial periodic signal at a decimated rate of a backplane clock, the backplane clock being asynchronous with a clock that generated the first clock signal; and means for constructing data blocks, each of one or more of the data blocks including a portion of the data signal and at least one sample of the initial periodic signal, and for providing the data blocks to a receiving device. 19. The system of claim 18 wherein the means for constructing the data blocks is further configured to construct the data blocks to include data from one or more terminals. 20. The system of claim 18 , wherein the means for constructing the data blocks comprises a Time Division Multiplexing (“TDM”) interface.

Assignees

Inventors

Classifications

  • concerning mainly a recovery circuit for the reference signal · CPC title

  • H04J3/0691Primary

    Synchronisation in a TDM node · CPC title

  • Synchronisation among TDM nodes · CPC title

  • Arrangements providing for calling or supervisory signals · CPC title

  • the loop being adapted to provide an additional control signal for use outside the loop · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9608754B2 cover?
A system may include a transmitting device. The transmitting device may include one or more terminals for receiving a data signal and a first clock signal. A first phase lock loop may lock a phase of an initial periodic signal with a phase of the first clock signal, the first phase lock loop including a divider to generate the initial periodic signal based on the first clock signal. A decimatio…
Who is the assignee on this patent?
Aviat Us Inc
What technology area does this patent fall under?
Primary CPC classification H04J3/0691. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).