Method and apparatus for decoding non-binary parity check code

Patent metadata

Field	Value
Publication number	US-9608667-B2
Application number	US-201414577033-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 27, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method of decoding a non-binary Low Density Parity Check (LDPC) code is provided. The method includes a plurality of messages to perform hard decision for all messages except for one message, and combines the hard-decided values with the one message that is not hard-decided, to update a final output message.

First claim

What is claimed is:

1. A method of decoding a non-binary low density parity check (LDPC) code, the method comprising:
receiving a plurality of messages from a plurality of variable nodes connected to a check node and hard-deciding the messages except for one message from a variable node among the plurality of variable nodes; and
combining the hard-decided values with the one message that is not hard-decided, to update a final output message.

2. The method of claim 1 , wherein the one message that is not hard-decided is determined to have a lowest reliability from a previously-defined reliability measurement vector.

3. The method of claim 2 , wherein the reliability measurement vector has a different value for each codeword symbol and a size of the reliability measurement vector is equal to a number of non-binary symbols of a single codeword.

4. The method of claim 2 , wherein, when the codeword symbol is hard-decided, values of the reliability measurement vector have a probability value that the codeword symbol is hard-decided for each of the non-binary symbols or a value corresponding thereto.

5. The method of claim 2 , wherein, when decoding fails, the reliability measurement vector is updated according to a predetermined rule until a decoding counter reaches a predetermined maximum value, and the hard decision is performed again.

6. An apparatus for decoding a non-binary low density parity check (LDPC) code, the apparatus comprising:
a hard decision unit configured to receive a plurality of messages from a plurality of variable nodes connected to a check node and hard-decide the messages except for one message from a variable node among the plurality of variable nodes; and
an output unit configured to combine the hard-decided values with the one message that is not hard-decided and update a final output message.

7. The apparatus of claim 6 , wherein the hard decision unit is further configured to determine that the one message that is not hard-decided has a lowest reliability from a previously-defined reliability measurement vector.

8. The apparatus of claim 7 , wherein the reliability measurement vector has a different value for each codeword symbol and a size of the reliability measurement vector is equal to a number of non-binary symbols of a single codeword.

9. The apparatus of claim 7 , wherein, when the codeword symbol is hard-decided, values of the reliability measurement vector have a probability value that the codeword symbol is hard-decided for each of the non-binary symbols or a value corresponding thereto.

10. The apparatus of claim 7 , further comprising a reliability measurement vector updating unit configured to:
update, when decoding fails, the reliability measurement vector according to a predetermined rule until a decoding counter reaches a predetermined maximum value,
wherein the hard decision unit is further configured to perform the hard decision on the basis of the updated reliability measurement vector.

Assignees

• Samsung Electronics Co Ltd
• Postech Academy-Industry Found

Inventors

• Myung Seho
• Kim Kyung-Joong
• Yang Kyeong-Cheol

Classifications

• H03M13/1171 Primary

  Parity-check or generator matrices with non-binary elements, e.g. for non-binary LDPC codes · CPC title

• H03M13/1117

  using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title

• H03M13/11 Primary

  using multiple parity bits · CPC title