Software programmable cellular radio architecture for wide bandwidth radio systems including telematics and infotainment systems

Patent metadata

Field	Value
Publication number	US-9608661-B2
Application number	US-201515103256-A
Country	US
Kind code	B2
Filing date	Nov 6, 2015
Priority date	Nov 6, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A cellular radio architecture that includes a programmable bandpass sampling radio frequency front-end and an optimized digital baseband. The architecture includes a multiplexer having signal paths that include a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals. The architecture also includes a receiver module having a separate signal channel for each of the signal paths in the multiplexer, where each signal channel in the receiver module includes a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals, where the transmitter module includes a power amplifier and a switch for directing the transmit signals to one of the signal paths in the multiplexer.

First claim

What is claimed is:

1. A transceiver front-end circuit for a cellular radio, said transceiver circuit comprising:
an antenna structure operable to transmit signals and receive signals;
a multiplexer coupled to the antenna structure and including a plurality of signal paths, each signal path including a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals;
a receiver module including a separate signal channel for each of the signal paths in the multiplexer, each signal channel in the receiver module including a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal; and
a transmitter module including a transmitter delta-sigma modulator for converting digital data bits to the transmit signals, said transmitter module including a tunable bandpass filter, a switch for directing the transmit signals to a particular signal path, and a power amplifier in each signal path for amplifying the transmit signal before transmitting.

2. The transceiver circuit according to claim 1 wherein each receiver delta-sigma modulator includes a low noise amplifier (LNA), an LC filter and a quantizer circuit, and wherein the quantizer circuit receives a filtered error signal from the LC filter and provides an estimation of the receive signal.

3. The transceiver circuit according to claim 2 wherein each signal path includes a combiner that receives the receive signals from the circulator and the estimation of the receive signal from the quantizer circuit and provides an error signal, said error signal being provided to the LC filter.

4. The transceiver circuit according to claim 2 wherein each signal channel includes a summation node that receives an amplified receive signal from the LNA and the estimation of the receive signal from the quantizer circuit and provides an error signal, said error signal being provided to the LC filter.

5. The transceiver circuit according to claim 2 wherein the LC filter is a sixth-order filter.

6. The transceiver circuit according to claim 5 wherein the LC filter includes a plurality of LC resonator circuits, a plurality of transconductance amplifiers and a plurality of integrator circuits, where a combination of one resonator circuit, transconductance amplifier and integrator circuit represents a two-order stage of the LC filter.

7. The transceiver circuit according to claim 6 wherein each LC circuit includes at least one inductor and a capacitor array where the capacitor array includes a plurality of capacitors controlled by switches that provide coarse and fine tuning.

8. The transceiver circuit according to claim 6 wherein the LC filter includes a low-speed digital-to-analog converter (DAC) array that receives coefficient control bits to control the integrator circuits.

9. The transceiver circuit according to claim 2 wherein the quantizer circuit is an interleaving quantizer circuit that interleaves multiple groups of bits from the filter.

10. The transceiver circuit according to claim 9 wherein the quantizer circuit includes a plurality of groups of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), wherein the ADCs receive the filtered error signal from the filter, and wherein the bits from the ADCs are provided to the DACs in the interleaving process, and wherein the output of the DACs is provided to the combiner.

11. The transceiver circuit according to claim 10 wherein the plurality of ADCs and DACs are 3-bit or 4-bit ADCs and DACs.

12. The transceiver circuit according to claim 2 wherein the quantizer circuit includes a data weighted averaging (DWA) digital shaper that modulates digital thermal codes to shape voltage and timing mismatches.

13. The transceiver circuit according to claim 2 wherein the LNA is a low noise transconductance amplifier (LNTA).

14. The transceiver circuit according to claim 1 wherein the transmitter module further includes a data weighted averaging (DWA) circuit that receives the transmit signals from the transmitter delta-sigma modulator and a digital-to-analog converter (DAC) that receives the transmit signals from the DWA circuit.

15. The transceiver circuit according to claim 14 wherein the DWA circuit modulates the digital thermal codes to shape out voltage and timing mismatch through DAC weighting elements, and wherein the DAC is a 4-bit DAC.

16. The transceiver circuit according to claim 14 wherein the transmitter delta-sigma modulator includes a dynamic element matching (DEM) circuit that employs an interleaving DEM algorithm.

17. The transceiver circuit according to claim 16 wherein a separate DEM circuit is provided for each bit of the DAC.

18. The transceiver circuit according to claim 1 wherein the transceiver circuit employs both silicon germanium (SiGe) and complementary metal oxide semiconductor (CMOS) technologies.

19. The transceiver circuit according to claim 18 wherein components and devices that operate at higher frequencies employ SiGe technologies and components and devices that operate at lower frequencies and employ CMOS technologies.

20. The transceiver circuit according to claim 19 wherein the filters employ SiGe technologies.

21. The transceiver circuit according to claim 19 wherein the SiGe and CMOS technologies are integrated using a micro-bump integration fabrication process.

22. The transceiver circuit according to claim 1 wherein the cellular radio is a vehicle cellular radio.

23. The transceiver circuit according to claim 1 wherein the multiplexer is a triplexer and the plurality of signal paths is three signal paths.

24. A transceiver front-end circuit for a vehicle cellular radio, said transceiver circuit comprising:
an antenna structure operable to transmit signals and receive signals;
a multiplexer coupled to the antenna structure and including a plurality of signal paths, each signal path including a bandpass filter that passes a different frequency band than the other bandpass filters and a circulator that provides signal isolation between the transmit signals and the receive signals;
a receiver module including a separate signal channel for each of the signal paths in the multiplexer, each signal channel in the receiver module including a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal, each receiver delta-sigma modulator including a low noise amplifier (LNA), an LC filter and a quantizer circuit, wherein the quantizer circuit receives a filtered error signal from the LC filter and provides an estimation of the receive signal, and wherein the quantizer circuit is an interleaving quantizer circuit that interleaves multiple groups of bits from the filter, and wherein the quantizer circuit includes a plurality of groups of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), wherein the ADCs receive the filtered error signal from the filter, and wherein the bits from the ADCs are provided to the DACs in the interleaving process, and wherein the output of the DACs is provided to the combiner; and
a transmitter module including a transmitter delta-sigma modulator for converting digital data bits to the transmit signals, said transmitter module including a tunable bandpass filter, a switch for directing the transmit signals to a particular signal path, and a power ampl

Assignees

• Gm Global Tech Operations Llc

Inventors

• Talty Timothy J
• Baringer Cynthia D
• Macdonald Andrew J
• Ahmed Mohiuddin
• Cosand Albert E
• Li James Chingwei
• Petre Peter
• Xu Zhiwei A
• Kuan Yen-Cheng
• Pan Hsuanyu
• Sovero Emilio A

Classifications

• H04B2001/0408

  with power amplifiers · CPC title

• H04B1/0007

  wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage · CPC title

• H03M3/424

  the quantiser being a multiple bit one · CPC title

• H04L1/0071

  Use of interleaving (interleaving per se H03M13/27) · CPC title

• H04B1/40

  Circuits · CPC title