Semiconductor device

Patent metadata

Field	Value
Publication number	US-9608639-B2
Application number	US-201514798854-A
Country	US
Kind code	B2
Filing date	Jul 14, 2015
Priority date	Jul 14, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A semiconductor device may include a delay line including a first group of unit delay cells and a second group of unit delay cells. The first group of unit delay cells and the second group of unit delay cells may be configured for delaying a phase of a clock by a unit cycle of a reference frequency. The reference frequency may serve as a reference for distinguishing between a first frequency and a second frequency. The semiconductor device may include a reservoir capacitor located adjacent to one or more of the unit delay cells of the first group. Only the first group of the unit delay cells may be used to delay the phase of the clock.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of delay lines each comprising a plurality of unit delay cells,
wherein the plurality of unit delay cells are divided into a first group of unit delay cells and a second group of unit delay cells, wherein the first group of the unit delay cells are used to delay a phase of a clock by a unit cycle of a reference frequency, and the second group of the unit delay cells are not used to delay the phase of the clock by the unit cycle of the reference frequency,
wherein the reference frequency serves as a reference for distinguishing between a first frequency and a second frequency, and
wherein the first frequency is a frequency higher than the reference frequency, and the second frequency is a frequency lower than the reference frequency, and
a reservoir capacitor selectively located adjacent to only one or more of the unit delay cells of the first group, and
wherein the one or more of the unit delay cells of the first group delays the clock having the first frequency.

2. The semiconductor device of claim 1 , wherein the reservoir capacitor is coupled between the first group of the unit delay cells and the second group of the unit delay cells.

3. The semiconductor device of claim 1 , wherein the reservoir capacitor is coupled between the unit delay cells of the first group.

4. The semiconductor device of claim 1 , wherein the unit delay cells of the first and second groups are arranged in a first direction along the longitudinal direction of the delay line.

5. The semiconductor device of claim 1 , wherein the reservoir capacitor comprises a MOS transistor type capacitor.

6. The semiconductor device of claim 5 , wherein the gate of the MOS transistor type capacitor is formed in a line shape extended along a direction substantially perpendicular to a longitudinal direction of the delay line.

7. The semiconductor device of claim 5 , wherein the gate of the MOS transistor type capacitor is formed in a line shape extended along a longitudinal direction of the delay line.

8. The semiconductor device of claim 1 , wherein the plurality of delay lines comprises:
a first delay line configured to delay a rising edge clock; and
a second delay line configured to delay a falling edge clock.

Assignees

• Sk Hynix Inc

Inventors

• Choi Hoon

Classifications

• H03L7/095

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/0818

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title