Semiconductor structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9608077-B1
Application number	US-201615048236-A
Country	US
Kind code	B1
Filing date	Feb 19, 2016
Priority date	Sep 4, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method for manufacturing a semiconductor structure includes preparing a semiconductor substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the semiconductor substrate in the memory cell region; forming a bit line structure over the semiconductor substrate in the memory cell region; forming a dielectric layer in the peripheral circuit region and the memory cell region; forming a first opening in the dielectric layer in the memory cell region; filling a silicon filler in the first opening; forming a second opening in the dielectric layer in the peripheral circuit region; forming a sidewall spacer over a sidewall of the second opening; recessing the silicon filler to form a silicon plug, wherein the silicon plug fills a lower portion of the first opening; and forming a first metal silicide over a top surface of the silicon plug, and concurrently forming a second metal silicide in a lower portion of the second opening.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
preparing a substrate which includes a first doping region and a second doping region;
forming a dielectric layer over the substrate;
forming a first opening in the dielectric layer to exposes the first doping region;
forming a silicon filler in the first opening;
forming a mask layer to protect the silicon filler and the first opening;
forming a second opening in the dielectric layer to exposes the second doping region, wherein the second opening is formed after the forming of the mask layer;
forming a sidewall spacer over the sidewall of the second opening;
recessing the silicon filler to form a silicon region, wherein the silicon region fills a lower portion of the first opening:
forming a first metal-silicon region over the silicon region; and
forming a second metal-silicon region over the second doping region.

2. The method according to claim 1 , further comprising:
forming a first metal region over the first metal-silicon region, and concurrently forming a second metal region over the second metal-silicon region.

3. The method according to claim 1 , wherein the first opening has an aspect ratio larger than the second opening.

4. The method according to claim 1 , wherein the first opening and the second opening have the same height, and
wherein the first opening has a width smaller than the second opening.

5. The method according to claim 1 , wherein the forming of the first metal-silicon region and the second metal-silicon region comprises:
forming a metal layer over the silicon region and the second doping region;
forming the first metal-silicon region by reacting the silicon region and the metal layer;
forming the second metal-silicon region by reacting the second doping region and the metal layer; and
removing a non-reacted metal layer.

6. The method according to claim 1 , further comprising:
Before the forming of the first metal-silicon region and the second metal-silicon region,
forming a first interface doping region over the silicon region; and
forming a second interface doping region over the second doping region.

7. The method according to claim 6 ,
wherein the silicon region is formed of a doped polysilicon layer,
wherein the first interface doping region has a doping concentration higher than the doped polysilicon layer, and
wherein the forming of the first interface doping region comprises:
doping an upper portion of the doped polysilicon layers to form the first interface doping region; and
performing a thermal processing to activate a dopant in the first interface doping region.

8. The method according to claim 6 ,
wherein the second interface doping region has a doping concentration higher than the second doping region, and
wherein the forming of the second interface doping region comprises:
doping an upper portion of the second doping region to form the second interface doping region; and
performing a thermal processing to activate a dopant in the second interface doping region.

9. The method according to claim 1 , wherein the first doping region comprises a source/drain region of a first transistor, and the second doping region comprises a source/drain region of a second transistor.

10. A method for manufacturing a semiconductor structure, comprising:
preparing a semiconductor substrate which includes a memory cell region and a peripheral circuit region;
forming a buried word line in the semiconductor substrate in the memory cell region;
forming a bit line structure over the semiconductor substrate in the memory cell region;
forming a dielectric layer over the semiconductor substrate in the peripheral circuit region and the bit line structure in the memory cell region;
forming a first opening in the dielectric layer in the memory cell region;
filling a silicon filler in the first opening;
forming a second opening in the dielectric layer in the peripheral circuit region;
forming a sidewall spacer over a sidewall of the second opening;
recessing the silicon filler to form a silicon plug, wherein the silicon plug fills a lower portion of the first opening; and
forming a first metal silicide over a top surface of the silicon plug, and concurrently forming a second metal silicide in a lower portion of the second opening,
wherein the forming of the second opening and the forming of the sidewall spacer comprises:
masking the memory cell region including the silicon filler;
forming the second opening by etching the dielectric layer in the peripheral circuit region;
forming a spacer layer to cover a sidewall and a bottom surface of the second opening; and
etching back the spacer layer to form the sidewall spacer over the sidewall of the second opening.

11. The method according to claim 10 , further comprising:
forming a first metal plug and a second metal plug concurrently,
wherein the first metal plug fills the first opening and is provided over the first metal silicide, and
wherein the second metal plug fills the second opening and is provided over the second metal silicide.

12. The method according to claim 10 , further comprising:
before the forming of the first metal silicide and the second metal silicide, doping a first dopant into the top surface of the silicon plug to form a first interface doping region.

13. The method according to claim 10 , further comprising:
before the forming of the first metal silicide and the second metal silicide, doping a second dopant into the semiconductor substrate exposed by the second opening to form a second interface doping region.

14. The method according to claim 10 , wherein the forming of the silicon plug comprises:
masking the peripheral circuit region including the second opening;
etching back the silicon filler and forming the silicon plug;
doping the top surface of the silicon plug with a dopant; and
performing a thermal processing to activate the dopant.

15. The method according to claim 10 , wherein the forming of the dielectric layer over the semiconductor substrate in the peripheral circuit region and the bit line in memory cell region comprises:
forming a interlayer dielectric layer over the bit line in the memory cell region and the semiconductor substrate in peripheral circuit region;
planarizing the interlayer dielectric layer such that a top surface of the bit line structure is exposed;
forming plug isolation parts by partially etching portions of the interlayer dielectric layer;
forming a plug isolation layer in the plug isolation parts; and
removing the remaining interlayer dielectric layer from the memory cell region,
wherein the interlayer dielectric layer remains in the peripheral circuit region, and the plug isolation layer is formed in the memory cell region.

16. The method according to claim 10 , further comprising:
forming a gate structure in the peripheral circuit region by using the same material as the bit line structure.

17. The method according to claim 16 , further comprising:
forming a first spacer element over a sidewall of the bit line structure; and
forming a second spacer element over a sidewall of the gate structure.

18. The method according to claim 17 , further comprising:
forming an air gap by removing a portion of the first spacer element; and
capping the air gap.

Assignees

• Sk Hynix Inc

Inventors

• Kye Jeong-Seob
• Kim Jae-Sung
• KIM Tae-Kyum
• Lee Kun-Young

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3822

  Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2923

  being conductive materials, e.g. metallic silicides · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title