Memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9608040-B2
Application number	US-201615158981-A
Country	US
Kind code	B2
Filing date	May 19, 2016
Priority date	Aug 21, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A memory device including a substrate, an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough, a first conductive pattern filling the first through hole, a second conductive pattern at least partially filling the second through hole, a magnetic tunnel junction pattern on the first conductive pattern, and a contact plug coupled to the second conductive pattern may be provided. Further, a method of fabricating the memory device also may be provided.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate;
an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface, the second top surface being lower than the first top surface with respect to the substrate, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough;
a first conductive pattern filling the first through hole;
a second conductive pattern at least partially filling the second through hole;
a magnetic tunnel junction pattern on the first conductive pattern; and
a contact plug coupled to the second conductive pattern.

2. The memory device of claim 1 , wherein a top surface of the second conductive pattern is one of substantially coplanar with and under the second top surface of the second region of the insulating layer.

3. The memory device of claim 1 , further comprising:
a protection pattern on the second conductive pattern.

4. The memory device of claim 3 , wherein the first conductive pattern includes a metallic material and the protection pattern includes a metallic oxide material.

5. The memory device of claim 3 , wherein a top surface of the protection pattern is one of substantially coplanar with and above the second top surface of the second region of the insulating layer.

6. The memory device of claim 1 , further comprising:
an insulating cover layer covering a sidewall of the magnetic tunnel junction pattern, which includes a first magnetic pattern, a second magnetic pattern, and a tunnel barrier pattern interposed therebetween.

7. A memory device, comprising:
a substrate;
an insulating layer on the substrate, the insulating layer including a first region having a first top surface and a second region having a second top surface recessed with respect to the first top surface, the first region including a first through hole penetrating therethrough, the second region including a second through hole penetrating therethrough;
a first conductive pattern filling the first through hole;
a second conductive pattern at least partially filling the second through hole;
a protection pattern on the second conductive pattern;
a magnetic tunnel junction pattern electrically connected to a top surface of the first conductive pattern; and
a contact plug electrically connected to a top surface of the second conductive pattern, while penetrating the protection pattern such that a residual portion of the protection pattern remains around a bottom portion of the contact plug.

8. The memory device of claim 7 , wherein the first conductive pattern includes a metallic material and the protection pattern includes a metallic oxide material.

9. The memory device of claim 7 , wherein the top surface of the second conductive pattern is one of substantially coplanar with and under the second top surface of the second region of the insulating layer.

10. The memory device of claim 7 , wherein a top surface of the protection pattern is one of substantially coplanar with and above the second top surface of the second region of the insulating layer.

11. The memory device of claim 7 , further comprising:
an insulating cover layer covering a sidewall of the magnetic tunnel junction pattern, the magnetic tunnel junction pattern including a first magnetic pattern, a second magnetic pattern, and a tunnel barrier pattern interposed therebetween,
wherein the insulating cover layer includes a same material as the protection pattern.

12. A magnetic memory device, comprising:
a substrate;
an insulating layer on the substrate, the insulating layer including a first region having a first top surface, a second region having a second top surface, and a third region having a third top surface, the third top surface being lower than the first and second top surfaces with respect to the substrate, the first, second, and third regions including first, second, and third through holes penetrating therethrough, respectively;
a first conductive pattern and a second conductive pattern filling the first and second through holes, respectively;
a third conductive pattern at least partially filling the third through hole;
a first magnetic tunnel junction pattern including a first electrode, a second electrode, and a first tunnel barrier pattern interposed therebetween, the first electrode electrically connected to the first conductive pattern;
a second magnetic tunnel junction pattern including a third electrode, a fourth electrode, and a second tunnel barrier pattern interposed therebetween, the third electrode electrically connected to the second conductive pattern; and
a contact plug electrically connected to the third conductive pattern.

13. The magnetic memory device of claim 12 , wherein:
the first and second electrodes of the first magnetic tunnel junction pattern are a fixed pattern and a free pattern of the first magnetic tunnel junction pattern, respectively; and
the third and fourth electrodes of the second magnetic tunnel junction pattern are a fixed pattern and a free pattern of the second magnetic tunnel junction pattern, respectively.

14. The magnetic memory device of claim 13 , further comprising:
a first bit line electrically connected to the free pattern of the first magnetic tunnel junction pattern; and
a second bit line connected to the fixed pattern of the second magnetic tunnel junction pattern.

15. The magnetic memory device of claim 13 , further comprising:
an interconnection pattern electrically connecting the free pattern of the second magnetic tunnel junction pattern to the contact plug.

16. The magnetic memory device of claim 12 , further comprising:
a first selection transistor electrically connected to the first conductive pattern; and
a second selection transistor electrically connected to the third conductive pattern.

17. The magnetic memory device of claim 16 , further comprising:
a common source line connected in common to source regions of both the first selection transistor and the second selection transistor.

18. The magnetic memory device of claim 12 , further comprising:
a protection pattern on the third conductive pattern.

19. The magnetic memory device of claim 18 , wherein the first and second conductive patterns include a metallic material, the protection pattern includes a metallic oxide material, and the contact plug is provided through the protection pattern such that the protection pattern remains at around a bottom portion of the third conductive pattern.

20. The magnetic memory device of claim 18 , wherein a top surface of the protection pattern is one of substantially coplanar with and above the third top surface of the third region of the insulating layer.

Assignees

• Baek Gwang-Hyun
• Kim Inho
• Kim Jong-Kyu
• Park Jongchul
• Oh Jung-Ik
• Samsung Electronics Co Ltd

Inventors

• Baek Gwang-Hyun
• Kim Inho
• Kim Jong-Kyu
• Park Jongchul
• Oh Jung-Ik

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L43/10

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L27/228 Primary

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic