Semiconductor device and wireless tag using the same

Patent metadata

Field	Value
Publication number	US-9607975-B2
Application number	US-201313874897-A
Country	US
Kind code	B2
Filing date	May 1, 2013
Priority date	Sep 19, 2008
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

In a wireless tag with which a wireless communication system whose electric power of a carrier wave from a R/W is high, an overvoltage protection circuit is provided to prevent from generating excessive electric power in the wireless tag when the wireless tag receives excessive electric power. However, as noise is generated by operation of the overvoltage protection circuit, an error of reception occurs in receiving a signal whose modulation factor is small. To solve the problem, the maximum value of generated voltage in the wireless tag is held in a memory circuit after the overvoltage protection circuit operates, then the overvoltage protection circuit is controlled in accordance with the maximum value of generated voltage. The voltages at which the overvoltage protection circuit starts and stops operating are different from each other, and hysteresis occurs between the timing when the overvoltage protection circuit starts and stops operating.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory circuit comprising a first transistor, a capacitor, and a second transistor; and
a protection circuit electrically connected to the memory circuit,
wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor and one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to the other electrode of the capacitor, and
wherein the second transistor comprises a semiconductor layer including indium and oxygen.

2. The semiconductor device according to claim 1 , further comprising a voltage detection circuit electrically connected to a gate of the second transistor and the other of the source and the drain of the second transistor.

3. The semiconductor device according to claim 1 , further comprising a voltage detection circuit electrically connected to a gate of the second transistor and the other of the source and the drain of the second transistor,
wherein the voltage detection circuit is configured to output a potential in accordance with a level of electric power supplied from an external portion, and
wherein the memory circuit is configured to hold a potential in accordance with a maximum value of the potential output from the voltage detection circuit.

4. The semiconductor device according to claim 1 ,
wherein the memory circuit includes a reset terminal,
wherein the memory circuit resets a potential which is held when a reset signal is input to the reset terminal, and
wherein the reset terminal is electrically connected to a gate of the first transistor.

5. The semiconductor device according to claim 1 , wherein the other electrode of the capacitor is held at a constant potential.

6. A semiconductor device comprising:
a memory circuit comprising a first transistor, a capacitor, and a second transistor; and
a protection circuit electrically connected to the memory circuit, the protection circuit comprising a third transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor,
wherein the other of the source and the drain of the first transistor is electrically connected to the other electrode of the capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the one of the source and the drain of the first transistor,
wherein a gate of the third transistor is electrically connected to the one electrode of the capacitor, and
wherein each of the second transistor and the third transistor comprises a semiconductor layer including indium and oxygen.

7. The semiconductor device according to claim 6 , further comprising a voltage detection circuit electrically connected to a gate of the second transistor and the other of the source and the drain of the second transistor.

8. The semiconductor device according to claim 6 , further comprising a voltage detection circuit electrically connected to a gate of the second transistor and the other of the source and the drain of the second transistor,
wherein the voltage detection circuit is configured to output a potential in accordance with a level of electric power supplied from an external portion, and
wherein the memory circuit is configured to hold a potential in accordance with a maximum value of the potential output from the voltage detection circuit.

9. The semiconductor device according to claim 6 ,
wherein the memory circuit includes a reset terminal,
wherein the memory circuit resets a potential which is held when a reset signal is input to the reset terminal, and
wherein the reset terminal is electrically connected to a gate of the first transistor.

10. The semiconductor device according to claim 6 , wherein the other electrode of the capacitor is held at a constant potential.

11. The semiconductor device according to claim 1 , further comprising an antenna circuit electrically connected to the protection circuit.

12. The semiconductor device according to claim 1 , further comprising:
an antenna circuit electrically connected to the protection circuit; and
a rectifier circuit electrically connected to the antenna circuit.

13. The semiconductor device according to claim 6 , further comprising an antenna circuit electrically connected to the protection circuit.

14. The semiconductor device according to claim 6 , further comprising:
an antenna circuit electrically connected to the protection circuit; and
a rectifier circuit electrically connected to the antenna circuit.

15. The semiconductor device according to claim 1 , wherein the semiconductor layer further comprises at least one of gallium and zinc.

16. The semiconductor device according to claim 1 , wherein the semiconductor layer further comprises gallium and zinc.

17. The semiconductor device according to claim 6 , wherein the semiconductor layer further comprises at least one of gallium and zinc.

18. The semiconductor device according to claim 6 , wherein the semiconductor layer further comprises gallium and zinc.

Assignees

• Semiconductor Energy Lab

Inventors

• Nishijima Tatsuji

Classifications

• G06K19/0715

  the arrangement including means to regulate power transfer to the integrated circuit · CPC title

• H01L27/0251 Primary

  Electricity · mapped topic

• G06K19/0712

  the arrangement being capable of triggering distinct operating modes or functions dependent on the strength of an energy or interrogation field in the proximity of the record carrier (active means for hindering electromagnetic reading or writing G06K19/07336) · CPC title

• G06K19/0707 Primary

  the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation (G06K19/0702 takes precedence) · CPC title

• G06K19/07749

  the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card · CPC title