Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Pin grid interposer
US9607937B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9607937-B2 |
| Application number | US-201113976194-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 19, 2011 |
| Priority date | Dec 19, 2011 |
| Publication date | Mar 28, 2017 |
| Grant date | Mar 28, 2017 |
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- Title
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Abstract
Official abstract text for this publication.
An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be pressed against pre-soldered pads and the solder reflowed to join the interposer to the package substrate. A top package (chip) is then joined to an opposite side of the interposer to integrate the first and second chips.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit (IC) package assembly, comprising: a bottom package including a first chip mounted to first interconnect pads on a first side of a bottom package substrate; and a pin grid interposer (PGI) forming a frame around the first chip and having pins projecting from a first side, the pins soldered to second interconnect pads disposed on the first side of the bottom package substrate, wherein a first dielectric layer is disposed around the sec…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9607937B2 cover?
- An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be…
- Who is the assignee on this patent?
- Watts Nicholas R, Wu Tao, Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W70/635. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).