Shift register group

Patent metadata

Field	Value
Publication number	US-9607712-B1
Application number	US-201615358939-A
Country	US
Kind code	B1
Filing date	Nov 22, 2016
Priority date	Mar 10, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

First claim

What is claimed is:

1. A shift register group, the shift register group comprising a plurality of series-coupled shift registers each being configured to provide an output signal, each one of the plurality of shift registers comprising:
a first output terminal, configured to provide the output signal;
a first output terminal control circuit, electrically coupled to the first output terminal and configured to receive a clock signal and determine whether to transmit the clock signal to the first output terminal or not according to a voltage at a driving node;
a first driving node control circuit, electrically coupled to the driving node and configured to receive a first control signal and determine whether to transmit the first control signal to the driving node or not according to a second control signal; and
a second driving node control circuit, electrically coupled to the driving node and configured to receive a third control signal and determine whether to transmit the third control signal to the driving node or not according to a fourth control signal,
wherein the third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number,
wherein the plurality of shift registers are divided into a plurality of groups each consisting of two shift registers, the two shift registers in the same group are corresponding to the same clock signal, an enable period of the clock signal corresponding to a specific group comprising the first shift register and an enable period of the clock signal corresponding to a group last the specific group partially overlap, and the enable period of the clock signal corresponding to the group last the specific group and an enable period of the clock signal corresponding to a group next the specific group do not overlap.

2. The shift register group according to claim 1 , wherein the second driving node control circuit comprises:
a transistor, comprising a control terminal, a first channel terminal and a second channel terminal, the transistor being configured to have the control terminal for receiving the fourth control signal, the first channel terminal electrically coupled to the driving node, and the second channel terminal for receiving the third control signal.

3. The shift register group according to claim 2 , wherein the first control signal of the first shift register is the output signal provided by the shift register N stages before the first shift register.

4. The shift register group according to claim 1 , wherein each one of the plurality of shift registers further comprises:
a second output terminal, configured to provide a startup signal; and
a second output terminal control circuit, electrically coupled to the second output terminal and configured to receive the clock signal and determine whether to transmit the clock signal to the second output terminal or not according to the voltage of the driving node.

5. A shift register group, the shift register group comprising a plurality of series-coupled shift registers coupled each being configured to provide an output signal, each one of the plurality of shift registers comprising:
a first output terminal, configured to provide the output signal;
a first output terminal control circuit, electrically coupled to the first output terminal and configured to receive a clock signal and determine whether to transmit the clock signal to the first output terminal or not according to a voltage at a driving node;
a first driving node control circuit, electrically coupled to the driving node and configured to receive a first control signal and determine whether to transmit the first control signal to the driving node or not according to a second control signal; and
a second driving node control circuit, electrically coupled to the driving node and configured to receive a third control signal and determine, according to a fourth control signal, whether to have the driving node for performing a specific operation in respond to the third control signal or not;
wherein the third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number, wherein the plurality of shift registers are divided into a plurality of groups each consisting of two shift registers, the two shift registers in the same group are corresponding to the same clock signal, an enable period of the clock signal corresponding to a specific group comprising the first shift register and an enable period of the clock signal corresponding to a group last the specific group partially overlap, and the enable period of the clock signal corresponding to the group last the specific group and an enable period of the clock signal corresponding to a group next the specific group do not overlap.

6. The shift register group according to claim 5 , wherein the second driving node control circuit comprises:
a transistor, comprising a control terminal, a first channel terminal and a second channel terminal, the transistor being configured to have the control terminal for receiving the fourth control signal, the first channel terminal electrically coupled to the driving node, and the second channel terminal for receiving the third control signal.

7. The shift register group according to claim 6 , wherein the first control signal of the first shift register is the output signal provided by the shift register N stages before the first shift register.

8. The shift register group according to claim 5 , wherein the first control signal of the first shift register is the output signal provided by the shift register N stages before the first shift register.

9. The shift register group according to claim 5 , wherein each one of the plurality of shift registers further comprises:
a second output terminal, configured to provide a startup signal; and
a second output terminal control circuit, electrically coupled to the second output terminal and configured to receive the clock signal and determine whether to transmit the clock signal to the second output terminal or not according to the voltage of the driving node.

Assignees

• Au Optronics Corp

Inventors

• Lin Wei-Li
• Tung Che-Wei
• Chen Chia-Heng

Classifications

• G09G5/003

  Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title