Non-volatile memory device, memory system, and methods of operating the device and system

Patent metadata

Field	Value
Publication number	US-9607700-B2
Application number	US-201615065906-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Apr 28, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

The method of operating a non-volatile memory device includes dumping data stored in input latches of a page buffer to other latches of the page buffer to receive second data to be written to a second cell group of a memory cell array from outside the non-volatile memory device during writing of first data to a first cell group of the memory cell array. In the method, receiving of the second data may be finished before the writing of the first data is finished.

First claim

What is claimed is:

1. A method of operating a non-volatile memory device including a memory cell array including a plurality of memory cells vertically stacked on a substrate and configured to respectively store n-bit data, and a page buffer configured to write data in parallel in m memory cells of the plurality of memory cells, wherein the page buffer comprises m latch modules, each of which comprises n latches including an input latch, and each of m and n is an integer equal to or greater than 2, the method of operating the non-volatile memory device comprising:
applying at least one pulse to a first cell group of the memory cell array to write first data stored in the m latch modules to the first cell group;
releasing m input latches of the m latch modules based on states of memory cells of the first cell group, which are changed according to the at least one pulse; and
transmitting second data to be written to a second cell group of the memory cell array in units of m-bit data to the m input latches;
wherein releasing of the m input latches comprises dumping data stored in the input latch of each of the m latch modules to another latch of the n latches.

2. The method of claim 1 , wherein releasing of the m input latches and transmitting of the m-bit data of the second data are performed n times during writing of the first data to the first cell group.

3. The method of claim 2 , wherein applying of the at least one pulse to the first cell group is performed at least n times until the writing of the first data is finished; and further comprising applying at least one pulse to the second cell group to write the second data stored in the m latch modules to the second cell group, after writing of the first data is finished.

4. The method of claim 3 , wherein when applying of the at least one pulse to the first cell group is performed first, the at least one pulse is applied to the first cell group based on data stored in at least two of the n latches of each of the m latch modules.

5. The method of claim 3 , further comprising inhibiting subsequent application of a pulse to a memory cell, which has reached a state corresponding to the first data due to the at least one pulse, from among the memory cells of the first cell group, during performing the at least n times the applying of the at least one pulse to the first cell group.

6. The method of claim 1 , wherein releasing of the m input latches further comprises outputting a release signal outside of the non-volatile memory device.

7. The method of claim 1 , wherein transmitting of the m-bit data of the second data comprises:
receiving m-bit data as part of the second data from outside the non-volatile memory device; and
transmitting the received m-bit data to the m released input latches.

8. The method of claim 1 , wherein dumping of the data stored in the input latch is performed during the transmitting of the m-bit data of the second data after first m-bit data of the second data is transmitted.

9. The method of claim 1 , wherein applying of the at least one pulse to the first cell group comprises applying at least one program pulse and at least one verification pulse to the first cell group; and wherein releasing of the m input latches is performed based on a verification result obtained due to the at least one verification pulse.

10. A method of operating a memory system comprising a non-volatile memory device and a memory controller configured to control the non-volatile memory device, wherein the non-volatile memory device comprises a memory cell array including a plurality of memory cells vertically stacked on a substrate, each memory cell configured to store n-bit data, and a page buffer configured to write data in parallel to m memory cells of the plurality of memory cells, and wherein the page buffer comprises m latch modules, each latch module comprising n latches including an input latch, and wherein each of m and n is an integer equal to or greater than 2, the method comprising:
applying at least one pulse to a first cell group of the memory cell array to write first data stored in the m latch modules to the first cell group in the non-volatile memory device;
releasing m input latches of the m latch modules based on states of memory cells of the first cell group, which are changed according to the at least one pulse in the non-volatile memory device;
outputting a release signal from the non-volatile memory device to the memory controller; and
transmitting m-bit data of second data to be written to a second cell group of the memory cell array to the non-volatile memory device in response to the release signal in the memory controller;
wherein releasing of the m input latches and transmitting of the m-bit data of the second data are performed at least twice during writing of the first data in the first cell group.

11. The method of claim 10 , further comprising transmitting the received m-bit data of the second data to the released m input latches in the non-volatile memory device; wherein releasing of the m input latches comprises dumping the data stored in the input latch to another latch of the n latches in each of the m latch modules.

12. The method of claim 11 , wherein dumping of the data stored in the input latch is performed during transmitting of the m-bit data of the second data after first m-bit data of the second data is transmitted.

13. The method of claim 10 , wherein releasing of the m latches and transmitting of the m-bit data of the second data are performed n times during writing of the first data to the first cell group.

14. The method of claim 13 , wherein applying of the at least one pulse to the first cell group is performed at least n times until the writing of the first data is finished; and further comprising applying at least one pulse to the second cell group in the non-volatile memory device to write the second data stored in the m latch modules to the second cell group, after writing of the first data is finished.

15. The method of claim 14 , wherein when applying of the at least one pulse to the first cell group is performed first, the at least one pulse is applied to the first cell group based on data stored in at least two of the n latches of each of the m latch modules.

16. A method of operating a memory system comprising a non-volatile memory device that includes a plurality of memory cells and a page buffer configured to write data to the plurality of memory cells, and wherein the page buffer comprises latch modules each comprising latches including an input latch, the method comprising:
applying at least one pulse to a first cell group of the plurality of memory cells to write first data stored in the latch modules to the first cell group in the non-volatile memory device;
releasing input latches of the latch modules based on states of memory cells of the first cell group which are changed according to the at least one pulse;
outputting a release signal from the non-volatile memory device; and
transmitting second data to be written to a second cell group of the plurality of memory cells to the non-volatile memory device in response to the release signal;
wherein releasing of the input latches and transmitting of the second data are performed at least twice during writing of the first data in the first cell group.

17. The method of claim 16 , further comprising transmitting the received second data to the released input latches in the non-volatile memory device; wherein releasing of the input latches comprises dumping the data stored in the input latch to another latch in ea

Assignees

• Kim Seung-Bum
• Samsung Electronics Co Ltd

Inventors

• Kim Seung-Bum

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C7/1087

  Data input latches · CPC title