EDRAM/DRAM fabricated capacitors for use in on-chip PMUS and as decoupling capacitors in an integrated EDRAM/DRAM and PMU system

Patent metadata

Field	Value
Publication number	US-9607680-B2
Application number	US-201414196793-A
Country	US
Kind code	B2
Filing date	Mar 4, 2014
Priority date	Mar 4, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. The capacitors may be physically placed near the logic components for which the capacitors are providing decoupling capacitance, in an embodiment. The capacitors may be series connections of at least two capacitors, or at least one capacitor and a switch, to provide decoupling capacitance in the face of defects, in an embodiment. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits.

First claim

What is claimed is:

1. A system comprising a plurality of integrated circuits, wherein at least a first integrated circuit of the plurality of integrated circuits is manufactured using a dynamic random access memory (DRAM) fabrication process, and wherein the first integrated circuit comprises:
a plurality of capacitors, wherein the plurality of capacitors provide decoupling capacitance for a plurality of components implemented on the first integrated circuit, wherein the plurality of capacitors comprises a first subset of capacitors including at least two capacitors connected in series between a power supply conductor and a ground conductor and a second subset of capacitors including only single capacitors connected between the power supply conductor and the ground conductor, and wherein the plurality of components comprise logic circuits coupled to the power supply conductor and the ground conductor, and wherein the first subset provides decoupling capacitance for a first component that experiences first transient current density during use, and wherein the second subset provides decoupling capacitance for a second component that experiences second transient current density during use, and wherein the second transient current density is greater than the first transient current density;
a plurality of power management units integrated into the first integrated circuit, wherein the plurality of power management units configured to provide a power supply on the power supply conductor to respective ones of the plurality of components; and
one or more of the plurality of capacitors is connected in series with a switch, wherein the series connection is between the power supply conductor and the ground conductor, and wherein the switch is open, during use, in response to a defect in a corresponding capacitor of the one or more of the plurality of capacitors.

2. The system as recited in claim 1 wherein the first integrated circuit further comprises the plurality of components.

3. The system as recited in claim 2 wherein the first integrated circuit further comprises a DRAM memory.

4. The system as recited in claim 1 wherein each of the plurality of power management units comprises a voltage regulator, wherein each voltage regulator comprises one or more capacitors formed using the DRAM fabrication process.

5. The system as recited in claim 1 wherein two or more of the plurality of integrated circuits including the first integrated circuit are implemented in a multi-chip module.

6. The system as recited in claim 1 wherein two or more of the plurality of integrated circuits including the first integrated circuit are stacked.

7. An integrated circuit manufactured using a dynamic random access memory (DRAM) fabrication process, and wherein the integrated circuit comprises:
a plurality of components that comprise logic circuits coupled to a power supply conductor and a ground conductor;
a plurality of capacitors, wherein the plurality of capacitors provide decoupling capacitance for a first component of the plurality of components and a second component of the plurality of components, and the plurality of capacitors is coupled between the power supply conductor and the ground conductor, and the first subset is physically placed between the first component and the second component; and
a plurality of power management units configured to supply power on the power supply conductor, wherein the decoupling capacitance supplied by the plurality of capacitors protects both the first component and the second component from transient current during use; and
one or more of the plurality of capacitors is connected in series with a switch, wherein the series connection is between the power supply conductor and the ground conductor, and wherein the switch is open, during use, in response to a defect in a corresponding capacitor of the plurality of capacitors.

8. The integrated circuit as recited in claim 7 further comprising a DRAM memory.

9. The integrated circuit as recited in claim 7 wherein the plurality of capacitors comprises at least two capacitors connected in series between a power supply conductor and a ground conductor.

Assignees

• Apple Inc

Inventors

• Dabral Sanjay

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title