Display apparatus having oblique lines and method of driving the same

Patent metadata

Field	Value
Publication number	US-9607581-B2
Application number	US-201414484239-A
Country	US
Kind code	B2
Filing date	Sep 11, 2014
Priority date	Mar 13, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Provided is a display device including: a display panel, a timing controller, a gate driver, and a data driver. The display panel includes a display area configured to display an image and a non-display area adjacent to one side of the display area. The display area includes oblique lines, intersectional lines crossing and isolated from at least a part of the oblique lines, and pixels. Pixels coupled to the oblique lines or the intersectional lines and arranged along a line in one direction are defined into pixel rows. The display area further includes a plurality of areas divided by the pixel rows being successive. The number of pixels constituting one of adjacent ones of the pixel rows in at least one of the plurality of areas is different from the number of pixels constituting another thereof.

First claim

What is claimed is:

1. A display device comprising:
a display panel comprising a display area configured to display an image and a non-display area adjacent to one side of the display area, the display area comprising oblique lines, intersectional lines crossing and isolated from at least a part of the oblique lines, and pixels, wherein pixels being coupled to one of the oblique lines or one of the intersectional lines and arranged along a line in one direction are defined into pixel rows;
a timing controller configured to receive a control signal and an input image signal, and to output a first control signal, a second control signal, and a data signal;
a gate driver configured to generate a gate signal based on the first control signal, and to output the gate signal to the oblique lines and the intersectional lines via the non-display area; and
a data driver configured to output a data voltage, obtained by converting the data signal, to the oblique lines and the intersectional lines via the non-display area in response to the second control signal,
wherein the display area further comprises a plurality of areas divided by the pixel rows being successive, and the number of pixels constituting one of adjacent ones of the pixel rows in at least one of the plurality of areas is different from the number of pixels constituting another thereof.

2. The display device of claim 1 , wherein the display panel has two adjacent edges extending in first and second directions that are different from each other,
wherein the oblique lines extend in a third direction, crossing the first and second directions, at one end of the display area adjacent to the non-display area, and
wherein the intersectional lines extend in a fourth direction, crossing the first, second, and third directions, at the one end of the display area.

3. The display device of claim 2 , wherein each of the oblique lines and the intersectional lines comprises at least one of gate lines extending in the third direction and data lines isolated from the gate lines and extending in the fourth direction.

4. The display device of claim 3 , wherein the display panel further comprises:
a contact portion coupling the gate lines and the data lines that are overlapped at both ends of the second direction of the display area when viewed from a top.

5. The display device of claim 4 , wherein the contact portion comprises:
a first contact portion at one end of the second direction of the display area; and
a second contact portion at another end of the second direction of the display area.

6. The display device of claim 5 , wherein the oblique lines comprise oblique hybrid lines comprising gate lines and data lines interconnected by the first contact portion, and oblique gate lines comprising a part of the gate lines, and
wherein the intersectional lines comprise intersectional hybrid lines comprising gate lines and data lines interconnected by the second contact portion, and intersectional data lines comprising a part of the data lines.

7. The display device of claim 6 , wherein the gate signal and the data voltage are applied to the oblique hybrid lines and the intersectional hybrid lines.

8. The display device of claim 6 , wherein a data voltage applied to a data line of each of the oblique hybrid lines and the intersectional hybrid lines has a first data voltage range, and a data voltage applied to a gate line of each of the oblique hybrid lines and the intersectional hybrid lines has a second data voltage range different from the first data voltage range.

9. The display device of claim 8 , wherein the second data voltage range is not overlapped with a range defined by a gate on voltage and a gate off voltage of the gate signal.

10. The display device of claim 1 , wherein the plurality of areas comprise:
an increasing area in which the number of pixels constituting each pixel row increases every pixel row;
a maintaining area in which the number of pixels constituting each pixel row is equal to one another; and
a decreasing area in which the number of pixels constituting each pixel row decreases every pixel row.

11. The display device of claim 10 , wherein pulse widths of gate signals applied to the pixel rows of the increasing area sequentially increase at least step by step, pulse widths of gate signals applied to the pixel rows of the decreasing area sequentially decrease at least step by step, and pulse widths of gate signals applied to the pixel rows of the maintaining area are equal to one another.

12. The display device of claim 10 , wherein pulse widths of gate signals applied to the pixel rows of the maintaining area are wider than pulse widths of gate signals applied to the pixel rows of the increasing area and pulse widths of gate signals applied to the pixel rows of the decreasing area.

13. The display device of claim 1 , wherein the pixels are configured to be driven by the pixel rows.

14. The display device of claim 13 , wherein the number of pixels configured to be driven during one of adjacent horizontal periods in at least one of the plurality of areas is different from the number of pixels configured to be driven during another thereof.

15. The display device of claim 1 , wherein the display panel further comprises:
thin film transistors coupled to the pixels and to two lines of the oblique lines and the intersectional lines.

16. The display device of claim 15 , wherein the data voltage has a first data voltage range, and each of the thin film transistors has a threshold voltage greater than an upper value of the first data voltage range.

17. The display device of claim 15 , wherein a data voltage applied to each of the pixels has a first data voltage range, and a data voltage applied to each of the oblique lines and the intersectional lines has a second data voltage range different from the first data voltage range.

18. The display device of claim 17 , wherein the second data voltage range is not overlapped with a range defined by a gate on voltage and a gate off voltage of the gate signal.

19. The display device of claim 1 , wherein the plurality of areas comprises a main area and a sub area that are driven independently within a same frame.

20. The display device of claim 19 , wherein the main area comprises a portion of the pixel rows coupled to at least one of two lines coupled to a first pixel row, from among the oblique lines and the intersectional lines, and
wherein the sub area comprises a remaining portion of the pixel rows that are not coupled to the two lines.

21. The display device of claim 19 , wherein a pixel row of the main area and a pixel row of the sub area that are configured to be driven during a same horizontal period are configured to receive a data voltage and a gate signal via different lines.

22. A display device comprising:
a display panel comprising a display area configured to display an image and a non-display area adjacent to one side of the display area, the display area comprising gate lines, data lines crossing and isolated from at least a part of the gate lines, and pixels, wherein pixels being coupled to one of the gate lines or one of the data lines and arranged along a line in one direction are defined into pixel rows;
a timing controller configured to receive a control signal and an input image signal, and to output a first control signal, a second control signal, and a data signal;
a gate driver configured to generate a gate signal based on the first control s

Assignees

• Samsung Display Co Ltd

Inventors

• Park Dong-Won
• Goh Joon-Chul
• You Bonghyun
• Lim Kyoungho
• Jeon Sangjin
• Jeong Junki

Classifications

• G09G5/18 Primary

  Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title

• G09G2310/0278

  Details of driving circuits arranged to drive both scan and data electrodes · CPC title