Apparatus and method for detecting clock tampering

Patent metadata

Field	Value
Publication number	US-9607153-B2
Application number	US-201313801375-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Disclosed is a method for detecting clock tampering. In the method a plurality of resettable delay line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times. A monotone signal is provided during a clock evaluate time period associated with a clock. The monotone signal is delayed using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals. The clock is used to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

First claim

What is claimed is:

1. A method for detecting clock tampering, comprising:
providing a plurality of resettable delay line segments, wherein resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times;
providing a monotone signal during a clock evaluate time period associated with a clock;
delaying the monotone signal using each of the plurality of resettable delay line segments to generate a respective plurality of delayed monotone signals each having either a one or a zero logic value; and
using the clock to trigger an evaluate circuit that uses the plurality of delayed monotone signals to detect a clock fault.

2. The method for detecting clock tampering as defined in claim 1 , further comprising:
resetting the resettable delay line segments during a reset time period, wherein the reset time period is prior to the clock evaluate time period.

3. The method for detecting clock tampering as defined in claim 1 , wherein using the clock to trigger the evaluate circuit comprises using a clock edge at an end of the clock evaluate time period to trigger the evaluate circuit.

4. The method for detecting clock tampering as defined in claim 1 , wherein the evaluate circuit determines whether the number of ones in the plurality of delayed monotone signals differs from a water level number by more than a predetermined threshold.

5. The method for detecting clock tampering as defined in claim 4 , wherein the water level number is determined based on delayed monotone signals from one or more previous clock evaluate time.

6. The method for detecting clock tampering as defined in claim 1 , wherein the plurality of resettable delay line segments comprises taps along a delay line.

7. The method for detecting clock tampering as defined in claim 1 , wherein the plurality of resettable delay line segments comprises parallel delay lines.

8. An apparatus for detecting clock tampering, comprising:
means for providing a monotone signal during a clock evaluate time period associated with a clock;
means for delaying the monotone signal to generate a plurality of delayed monotone signals having discretely increasing delay times between a minimum delay time and a maximum delay time and each of the plurality of delayed monotone signals having either a one or a zero logic value;
means for evaluating that uses the plurality of delayed monotone signals to detect a clock fault and
means for triggering the means for evaluating.

9. The apparatus for detecting clock tampering as defined in claim 8 , further comprising:
means for resetting the means for delaying the monotone signal during a reset time period, wherein the reset time period is prior to the clock evaluate time period.

10. The apparatus for detecting clock tampering as defined in claim 8 , wherein the means for triggering the means for evaluating uses a clock edge at an end of the clock evaluate time period to trigger the means for evaluating.

11. The apparatus for detecting clock tampering as defined in claim 8 , wherein-the means for evaluating determines whether the number of ones in the plurality of delayed monotone signals differs from a water level number by more than a predetermined threshold.

12. The apparatus for detecting clock tampering as defined in claim 11 , wherein the water level number is determined based on delayed monotone signals from one or more previous clock evaluate time.

13. The apparatus for detecting clock tampering as defined in claim 8 , wherein the means for delaying the monotone signal includes taps along a delay line.

14. The apparatus for detecting clock tampering as defined in claim 8 , wherein the means for delaying the monotone signal includes parallel delay lines.

15. An apparatus for detecting clock tampering, comprising:
a circuit that provides a monotone signal during a clock evaluate time period associated with a clock;
a plurality of resettable delay line segments that delay the monotone signal to generate a respective plurality of delayed monotone signals each having either a one or a zero logic value, wherein resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times; and
an evaluate circuit, triggered by the clock, that uses the plurality of delayed monotone signals to detect a clock fault.

16. The apparatus for detecting clock tampering as defined in claim 15 , wherein the resettable delay line segments are reset during a reset time period, wherein the reset time period is prior to the clock evaluate time period.

17. The apparatus for detecting clock tampering as defined in claim 15 , wherein the evaluate circuit is triggered by a clock edge at an end of the clock evaluate time period.

18. The apparatus for detecting clock tampering as defined in claim 15 , wherein the evaluate circuit determines whether the number of ones in the plurality of delayed monotone signals differs from a water level number by more than a predetermined threshold to detect a clock fault.

19. The apparatus for detecting clock tampering as defined in claim 18 , wherein the water level number is determined based on delayed monotone signals from one or more previous clock evaluate time.

20. The apparatus for detecting clock tampering as defined in claim 15 , wherein the plurality of resettable delay line segments comprises taps along a delay line.

21. The apparatus for detecting clock tampering as defined in claim 15 , wherein the plurality of resettable delay line segments comprises parallel delay lines.

22. An apparatus for detecting clock tampering, comprising:
a first circuit that provides a first monotone signal during a first clock evaluate time period associated with a clock;
a first plurality of resettable delay line segments that each delay the first monotone signal to generate a respective first plurality of delayed monotone signals, wherein resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times;
a second circuit that provides a second monotone signal during a second clock evaluate time period associated with the clock, wherein the second clock evaluate time period covers a different time than the first clock evaluate time period;
a second plurality of resettable delay line segments that each delay the second monotone signal to generate a respective second plurality of delayed monotone signals, wherein resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a resettable delay line segment associated with a maximum delay time are each associated with discretely increasing delay times; and
an evaluate circuit, triggered by the clock, that uses the first plurality of delayed monotone signals or the second plurality of delayed monotone signals to detect a clock fault.

23. A method for detecting voltage tampering, comprising:
providing a plurality of resettable delay line segments, wherein resettable delay line segments between a resettable delay line segment associated with a minimum delay time and a rese

Assignees

• Qualcomm Inc

Inventors

• Tiri Kris
• Mcgregor Matthew Scott
• Tao Yucong

Classifications

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F21/725

  operating on a secure reference time value · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F21/70

  Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer · CPC title