Instruction and logic for a binary translation mechanism for control-flow security

Patent metadata

Field	Value
Publication number	US-9606941-B2
Application number	US-201615140427-A
Country	US
Kind code	B2
Filing date	Apr 27, 2016
Priority date	Mar 27, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.

First claim

What is claimed is:

1. A processor, comprising:
a front end including circuitry to receive an instruction and to dispatch the instruction to a binary translator;
an execution pipeline; and
a binary translator including circuitry to:
determine whether the instruction includes a control-flow instruction;
identify a source address of the instruction;
identify a target address of the instruction, the target address including an address to which execution would indirectly branch upon execution of the instruction;
determine whether the target address is a known destination based upon the source address; and
determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address.

2. The processor of claim 1 , wherein the binary translator further includes circuitry to:
access a control structure with references of a set of known destinations for the source address; and
determine whether the target address is identified with the set of known destinations.

3. The processor of claim 1 , wherein the binary translator further includes circuitry to:
access a control structure with no known destinations for the source address; and
determine to not route the instruction to the execution pipeline based on a determination that there are no known destinations for the source address.

4. The processor of claim 1 , wherein the binary translator further includes circuitry to:
access a control structure with references of a set of known destinations for each of a set of given source addresses;
access a default set of known destinations based on a determination that there is no entry in the control structure for the source addresses; and
determine whether to route the instruction to the execution pipeline based upon whether the target address is included in the default set of known destinations.

5. The processor of claim 1 , wherein the binary translator further includes circuitry to route another instruction to the execution pipeline based upon a determination that the other instruction does not include a control-flow instruction.

6. The processor of claim 1 , wherein the binary translation further includes circuitry to:
access a control structure with references of a set of known destinations for each of a set of given source addresses;
determine that the target address is not within the set of known destinations for the source address;
generate an exception based upon the determination that the target address is not within the set of known destinations for the source address.

7. The processor of claim 1 , wherein the binary translation further includes circuitry to:
access a control structure with entries for a plurality of given source addresses, wherein each entry defines:
whether any known destinations are available for a given source address;
a size of a list of known destinations; and
an offset to a memory segment for the list of known destinations;

access the memory segment based upon the offset; and
determine whether the target address is within the list of known destinations.

8. A system, comprising:
a front end including circuitry to receive an instruction and to dispatch the instruction to a binary translator;
an execution pipeline; and
a binary translator including circuitry to:
determine whether the instruction includes a control-flow instruction;
identify a source address of the instruction;
identify a target address of the instruction, the target address including an address to which execution would indirectly branch upon execution of the instruction;
determine whether the target address is a known destination based upon the source address; and
determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address.

9. The system of claim 8 , wherein the binary translator further includes circuitry to:
access a control structure with references of a set of known destinations for the source address; and
determine whether the target address is identified with the set of known destinations.

10. The system of claim 8 , wherein the binary translator further includes circuitry to:
access a control structure with no known destinations for the source address; and
determine to not route the instruction to the execution pipeline based on a determination that there are no known destinations for the source address.

11. The system of claim 8 , wherein the binary translator further includes circuitry to:
access a control structure with references of a set of known destinations for each of a set of given source addresses;
access a default set of known destinations based on a determination that there is no entry in the control structure for the source addresses; and
determine whether to route the instruction to the execution pipeline based upon whether the target address is included in the default set of known destinations.

12. The system of claim 8 , wherein the binary translator further includes circuitry to route another instruction to the execution pipeline based upon a determination that the other instruction does not include a control-flow instruction.

13. The system of claim 8 , wherein the binary translation further includes circuitry to:
access a control structure with references of a set of known destinations for each of a set of given source addresses;
determine that the target address is not within the set of known destinations for the source address;
generate an exception based upon the determination that the target address is not within the set of known destinations for the source address.

14. The system of claim 8 , wherein the binary translation further includes circuitry to:
access a control structure with entries for a plurality of given source addresses, wherein each entry defines:
whether any known destinations are available for a given source address;
a size of a list of known destinations; and
an offset to a memory segment for the list of known destinations;

access the memory segment based upon the offset; and
determine whether the target address is within the list of known destinations.

15. At least one non-transitory machine readable storage medium, comprising computer-readable instructions carried on the machine readable medium, the instructions readable by a hardware processor, the instructions, when read and executed, for causing the processor to perform:
receiving an instruction;
determining whether the instruction includes a control-flow instruction;
identifying a source address of the instruction;
identifying a target address of the instruction, the target address including an address to which execution would indirectly branch upon execution of the instruction;
determining whether the target address is a known destination based upon the source address; and
determining whether to route the instruction to an execution pipeline based upon the determination whether the target address is a known destination based upon the source address.

16. The at least one non-transitory machine readable storage medium of claim 15 , further comprising instructions to cause the processor to perform:
accessing a control structure with references of a set of known destinations for the source address; and
determining whether the target address is identified with the set of known destinations.

17. The at least one non-transitory machine readable storage medium of claim 15 , further compris

Assignees

• Intel Corp

Inventors

• Maniatis Petros
• Gupta Shantanu
• Kumar Naveen

Classifications

• G06F13/1615

  using a concurrent pipeline structrure · CPC title

• G06F21/52

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F9/3017

  Runtime instruction translation, e.g. macros · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title