Method and apparatus to facilitate shared pointers in a heterogeneous platform

Patent metadata

Field	Value
Publication number	US-9606919-B2
Application number	US-201414513065-A
Country	US
Kind code	B2
Filing date	Oct 13, 2014
Priority date	Mar 29, 2011
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

First claim

What is claimed is:

1. One or more non-transitory computer readable media having instructions thereon that, in response to execution by a second processing device of a computer device having a first and the second processing device, cause the second processing device of the computer device to:
receive, from the first processing device, a first pointer to a memory location of the computer device, wherein the memory location resides in a region of a memory that is accessible by both the first processing device and the second processing device, wherein the first pointer is not in a format usable by the second processing device to access the memory location;
generate a second pointer, by the second processing device, based on the first pointer, that is in the format usable by the second processing device to access the memory location; and
access the memory location, by the second processing device, using the second pointer.

2. The one or more non-transitory computer readable media of claim 1 , wherein the first pointer has a different length than the second pointer.

3. The one or more non-transitory computer readable media of claim 1 , wherein the first pointer encodes the memory location in accordance with a first technique and the second pointer encodes the memory location in accordance with a second technique different from the first technique.

4. The one or more non-transitory computer readable media of claim 3 , wherein the first technique or the second technique encodes the memory location based on a binding table index and an offset.

5. The one or more non-transitory computer readable media of claim 3 , wherein the first technique or the second technique encodes the memory location based on a base address of the shared memory region and a memory address of a pointer in the shared memory region.

6. The one or more non-transitory computer readable media of claim 1 , wherein the first pointer is received as an argument of a function.

7. The one or more non-transitory computer readable media of claim 1 , wherein the computer device includes a compiler having logic to generate the second pointer.

8. A method for accessing memory shared by a first and a second processing device on a computing device, comprising:
receiving, by the second processing device, from the first processing device, a first pointer to a memory location of the computing device, wherein the memory location resides in a region of a memory that is accessible by both the first processing device and the second processing device, wherein the first pointer is not in a format usable by the second processing device to access the memory location;
generating a second pointer, by the second processing device, based on the first pointer, that is in the format usable by the second processing device to access the memory location; and
accessing, by the second processing device, the memory location, using the second pointer.

9. The method of claim 8 , wherein the first pointer has a different length than the second pointer.

10. The method of claim 8 , wherein the first pointer encodes the memory location in accordance with a first technique and the second pointer encodes the memory location in accordance with a second technique different from the first technique.

11. The method of claim 10 , wherein the first technique or the second technique encodes the memory location based on a binding table index and an offset.

12. The method of claim 11 , wherein the first technique or the second technique encodes the memory location based on a base address of the shared memory region and a memory address of a pointer in the shared memory region.

13. The method of claim 8 , wherein the first pointer is received as an argument of a function.

14. A computer device, comprising:
a first and a second processing device; and
a memory;
wherein the second processing device is to:
receive, from the first processing device, a first pointer to a location of the memory, wherein the memory location resides in a region of the memory that is accessible by both the first processing device and the second processing device, wherein the first pointer is not in a format usable by the second processing device to access the memory location;
generate a second pointer, based on the first pointer, that is in the format usable by the second processing device to access the memory location; and
access the memory location using the second pointer.

15. The computer device of claim 14 , wherein the first pointer has a different length than the second pointer.

16. The computer device of claim 14 , wherein the first pointer encodes the memory location in accordance with a first technique and the second pointer encodes the memory location in accordance with a second technique different from the first technique.

17. The computer device of claim 14 , wherein the first pointer is received as an argument of a function.

Assignees

• Intel Corp

Inventors

• Ni Yang
• Barik Rajkishore
• Adl-Tabatabai Ali-Reza
• Shpeisman Tatiana
• Rao Jayanth N
• Ashbaugh Ben J
• Janczak Tomasz

Classifications

• G06F15/167 Primary

  using a common memory, e.g. mailbox · CPC title

• G06F12/0806 Primary

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title

• G06T1/60

  Memory management · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title