Semiconductor devices including application processor connected to high-bandwidth memory and low-bandwidth memory, and channel interleaving method thereof

Patent metadata

Field	Value
Publication number	US-9606916-B2
Application number	US-201414307994-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Sep 13, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

First claim

What is claimed is:

1. A system on chip (SoC) comprising:
a high-bandwidth memory device having a plurality of access channels;
a first low-bandwidth memory device having one or more access channels, the high-bandwidth memory device having a higher operation bandwidth than the first low-bandwidth memory device; and
an interleaving unit configured to perform a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and at least one of the one or more access channels of the first low-bandwidth memory device,
wherein the interleaving unit comprises:
a high-bandwidth channel interleaver in communication with the high-bandwidth memory device and the first low-bandwidth memory device and configured to manage a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and configured to manage the memory interleave operation among the plurality of access channels of the high-bandwidth memory device and the at least one of the one or more access channels of the first low-bandwidth memory device,
a low-bandwidth channel interleaver configured to manage the memory interleave operation among the remaining access channels of the first low-bandwidth memory device other than the at least one access channel of the first low-bandwidth memory device managed by the high-bandwidth channel interleaver, and
a router configured to receive a request for a channel interleaving and configured to designate one of access to a high-bandwidth region and a low-bandwidth region,
wherein, when the router designates access to the high-bandwidth region, the high-bandwidth channel interleaver is selected, when the router designates access to the low-bandwidth region, the low-bandwidth channel interleaver is selected, and, when the router extends the high-bandwidth region, the router extends the high-bandwidth region to include a path to the at least one access channel of the low-bandwidth memory device.

2. The SoC of claim 1 , wherein the interleaving unit comprises a memory controller in communication with the high-bandwidth memory device and the first low-bandwidth memory device.

3. The SoC of claim 1 , wherein the first low-bandwidth memory device comprises a plurality of access channels, and the interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and the plurality of access channels of the first low-bandwidth memory device.

4. The SoC of claim 1 , wherein the interleaving unit performs a mode of operation of the SoC among one of:
an interleave operation among the plurality of access channels of the high-bandwidth memory device;
an interleave operation among the one or more access channels of the first low-bandwidth memory device; and
an interleave operation among the plurality of access channels of the high-bandwidth memory and the at least one of the one or more access channels of the first low-bandwidth memory device.

5. The SoC of claim 1 further comprising a second low-bandwidth memory device, and
wherein the second low-bandwidth memory device includes one or more access channels, and
the memory interleave operation is performed among the plurality of access channels of the high-bandwidth memory device, the at least one of one or more access channels of the first low-bandwidth memory device, and at least one of the one or more access channels of the second low-bandwidth memory device.

6. The SoC of claim 1 :
wherein the high-bandwidth memory device comprises a Wide I/O memory device; and
wherein the low-bandwidth memory device comprises a Low-Power DDR (LPDDR) memory device.

7. The SoC of claim 6 , wherein, during a low-power mode of operation of the SoC, the interleaving unit performs the memory interleave operation among the plurality of access channels of the Wide I/O memory device.

8. The SoC of claim 7 , wherein, during a high-power mode of operation of the SoC, the interleaving unit performs the memory interleave operation among the plurality of access channels of the Wide I/O memory device and the at least one of the one or more access channels of the LPDDR memory device.

9. The SoC of claim 1 , wherein a bandwidth of the high-bandwidth memory device is evenly divided by the number of access channels of the high-bandwidth memory device, and the high-bandwidth memory device performs data communication via each access channel with the evenly divided bandwidth.

10. The SoC of claim 9 , wherein a bandwidth of the low-bandwidth memory device is evenly divided by the number of access channels of the low-bandwidth memory device, and when the evenly divided bandwidth of the low-bandwidth memory device is less than the evenly divided bandwidth of the high-bandwidth memory device, the interleaving unit performs a portion of a memory access command using at least two access channels of the low-bandwidth memory device.

11. The SoC of claim 1 , wherein the high-bandwidth memory device is fabricated on a first chip,
an application processor including the interleaving unit is fabricated on a second chip, and
the first chip and the second chip are connected to one another using a through-silicon via connection arrangement.

12. The SoC of claim 11 :
wherein the first chip and second chip are mounted to a first printed circuit board and packaged collectively in a first chip package, the low-bandwidth memory device is fabricated on a third chip mounted to a second printed circuit board,
the third chip is connected to the second printed circuit board by a wiring arrangement,
the third chip and the second printed circuit board are packaged collectively in a second package; and the first chip package and the second chip package are connected to each other by a wiring arrangement.

13. A system on chip (SoC) comprising:
a memory controller;
a high-bandwidth memory device in communication with the memory controller, the high-bandwidth memory device having a plurality of access channels, the high-bandwidth memory device comprising a Wide I/O type memory device;
a low-bandwidth memory device in communication with the memory controller, the low-bandwidth memory device having one or more access channels, the low-bandwidth device comprising a Low-Power DDR type memory device, the high-bandwidth memory device having a higher operation bandwidth than the first low-bandwidth memory device; and
an interleaving unit configured to perform a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and at least one of the one or more access channels of the low-bandwidth memory device,
wherein, during a low-power mode of operation of the SoC, the interleaving unit performs the memory interleave operation among only the plurality of access channels of the high-bandwidth memory device,
wherein the interleaving unit comprises a router configured to receive a request for a channel interleaving and configured to designate one of access to a high-bandwidth region and a low-bandwidth region,
wherein, when the router designates access to the high-bandwidth region, the plurality of access channels of the high-bandwidth memory device are selected, when the router designates access to the low-bandwidth region, the one or more access channels of the low-bandwidth channel interleaver are selected, and, when the router extends the high-bandwidth region, the router extends the high-bandwidth region to include a path to the at least one access channel of the low-bandwidth memory device.

14. The SoC of claim 13 further comprising:
a first chip on which the memory co

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sung Hyun
• Yoo Jun Hee
• Kang Dongsoo
• Park Il
• Lee Kiyeon
• Lim Euicheol

Classifications

• G06F12/0607 Primary

  Interleaved addressing · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title