Tracing data from an asynchronous interface

Patent metadata

Field	Value
Publication number	US-9606891-B2
Application number	US-201514733249-A
Country	US
Kind code	B2
Filing date	Jun 8, 2015
Priority date	Jun 12, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

An apparatus for tracing data from a data bus in a first clock domain operating at a first clock frequency to a trace array in a second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency. The apparatus includes a change detector to detect a change of the data on the data bus in the first clock domain, a trigger responsive to the change detector to send a trigger pulse to the second clock domain, pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse to the second clock frequency of the second clock domain by a meta-stability latch, as well as a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.

First claim

What is claimed is:

1. An apparatus for tracing data from a data bus in a first clock domain to a trace array in a second clock domain, said apparatus comprising:
a change detector to detect a change of the data on the data bus in the first clock domain, the first clock domain operating at a first clock frequency;
a trigger responsive to the change detector to send a trigger pulse from the first clock domain to the second clock domain signaling new data available on the data bus, and the trigger pulse being provided to the second clock domain unsynchronized to the second clock domain, the second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency;
a pulse synchronization on the second clock domain responsive to the trigger pulse to synchronize the trigger pulse from the first clock domain to the second clock frequency of the second clock domain by a meta-stability latch; and
a data capture in the second clock domain responsive to the pulse synchronization to capture data from the data bus and to store the captured data in the trace array.

2. The apparatus according to claim 1 , wherein the data changes its value not faster than every four cycles of the first clock frequency.

3. The apparatus according to claim 1 , wherein data capturing with the pulse synchronization is operating at the second clock frequency, and wherein storing the captured data into the trace array is performed at half of the second clock frequency.

4. The apparatus according to claim 1 , wherein the apparatus is configured such that the data flows from the first clock domain to the second clock domain.

5. The apparatus according to claim 1 , wherein the change detector comprises an EXCLUSIVE-OR (XOR) circuit.

6. The apparatus according to claim 1 , wherein the pulse synchronization comprises a programmable delay for synchronization of the data capture.

7. The apparatus according to claim 6 , wherein data capturing is controllable by the programmable delay of the pulse synchronization.

8. The apparatus according to claim 1 , wherein the data capture allows a direct capture of tracing data from the first clock domain.

9. A method of tracing data from a data bus in a first clock domain to a trace array in a second clock domain, the method comprising:
detecting a change of the data on the data bus of the first clock domain by a change detector, the first clock domain operating at a first clock frequency;
sending a trigger pulse from the first clock domain to the second clock domain responsive to the change detector, the trigger pulse signaling new data available on the data bus, and the trigger pulse being provided to the second clock domain unsynchronized to the second clock domain, the second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency;
synchronizing the trigger pulse from the first clock domain to the second clock frequency of the second clock domain by a meta-stability latch by pulse synchronization of the second clock domain, the pulse synchronization being responsive to the trigger pulse; and
capturing data from the data bus and storing the captured data in the trace array by a data capture on the second clock domain, the data capture being responsive to the pulse synchronization.

10. The method according to claim 9 , wherein the data changes its value not faster than every four cycles of the first clock frequency.

11. The method according to claim 9 , wherein data capturing with the pulse synchronization is operating at the second clock frequency, and wherein storing the captured data into the trace array is performed at half of the second clock frequency.

12. The method according to claim 9 , wherein the pulse synchronization comprises a programmable delay for synchronization of the data capture.

13. The method according to claim 9 , wherein the data flows from the first clock domain to the second clock domain.

14. The method according to claim 9 , wherein the change detector comprises an EXCLUSIVE-OR (XOR) circuit.

15. A computer program product for tracing data from a data bus in a first clock domain to a trace array in a second clock domain, said computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
detecting a change of the data on the data bus of the first clock domain by a change detector, the first clock domain operating at a first clock frequency;
sending a trigger pulse from the first clock domain to the second clock domain responsive to the change detector, the trigger pulse signaling new data available on the data bus, and the trigger pulse being provided to the second clock domain unsynchronized to the second clock domain, the second clock domain operating at a second clock frequency, wherein the first clock frequency is lower than the second clock frequency;
synchronizing the trigger pulse from the first clock domain to the second clock frequency of the second clock domain by a meta-stability latch by pulse synchronization of the second clock domain, the pulse synchronization being responsive to the trigger pulse; and
capturing data from the data bus and storing the captured data in the trace array by a data capture on the second clock domain, the data capture being responsive to the pulse synchronization.

16. The computer program product according to claim 15 , wherein the data changes its value not faster than every four cycles of the first clock frequency.

17. The computer program product according to claim 15 , wherein the data flows from the first clock domain to the second clock domain.

18. The computer program product according to claim 15 , wherein the change detector comprises an EXCLUSIVE-OR (XOR) circuit.

19. The computer program product according to claim 15 , wherein the pulse synchronization comprises a programmable delay for synchronization of the data capture.

Assignees

• IBM

Inventors

• Hagspiel Norbert
• Junghans Sascha
• Klein Matthias
• Walter Joerg

Classifications

• G06F11/3027

  where the computing system component is a bus · CPC title

• G06F11/348 Primary

  Circuit details, i.e. tracer hardware · CPC title

• G06F13/14

  Handling requests for interconnection or transfer · CPC title

• G06F5/06

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title