Method and apparatus for sharing instruction scheduling resources among a plurality of execution threads in a multi-threaded processor architecture

Patent metadata

Field	Value
Publication number	US-9606800-B1
Application number	US-201313836145-A
Country	US
Kind code	B1
Filing date	Mar 15, 2013
Priority date	Mar 15, 2012
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A microprocessor includes a front end module and a schedule queue module. The front end module is configured to retrieve first instructions, corresponding to a first thread, from an instruction cache, and retrieve second instructions, corresponding to a second thread, from the instruction cache. The front end module is also configured to decode the first instructions into first decoded instructions, and decode the second instructions into second decoded instructions. The schedule queue module is configured to selectively store the first decoded instructions and the second decoded instructions from the front end module and, for each stored decoded instruction, selectively issue the stored decoded instruction to an execution module. The schedule queue is further configured to reject storing an additional one of the first decoded instructions from the front end module in response to a count of the stored first decoded instructions in the schedule queue module exceeding a threshold.

First claim

What is claimed is:

1. A microprocessor comprising:
a front end module configured to
retrieve first instructions, corresponding to a first thread, from an instruction cache,
retrieve second instructions, corresponding to a second thread, from the instruction cache,
decode the first instructions into first decoded instructions, and
decode the second instructions into second decoded instructions; and

a schedule queue module configured to
selectively store the first decoded instructions and the second decoded instructions from the front end module for future issuance, and
for each stored decoded instruction, selectively issue the stored decoded instruction to an execution module,

wherein the schedule queue module is configured to reject storing an additional one of the first decoded instructions from the front end module in response to a count of the stored first decoded instructions in the schedule queue module exceeding a first threshold,
wherein the first threshold is smaller than a total number of instructions that the schedule queue module is capable of storing, and
wherein the first threshold is based on a difference between (i) the total number of instructions and (ii) a total number of threads serviced by the front end module.

2. The microprocessor of claim 1 , wherein the schedule queue module is configured to, for each stored decoded instruction, issue the stored decoded instruction to the execution module in response to dependencies being resolved for the stored decoded instruction.

3. The microprocessor of claim 1 , wherein the schedule queue module is configured to reject storing an additional one of the second decoded instructions in response to a count of the stored second decoded instructions in the schedule queue module exceeding the first threshold.

4. The microprocessor of claim 1 , further comprising the execution module, wherein the execution module comprises an arithmetic logic unit or a memory access unit.

5. The microprocessor of claim 1 , wherein the schedule queue module is configured to flush the stored first decoded instructions in response to both (i) the stored first decoded instructions experiencing a stall condition and (ii) the count of the stored first decoded instructions in the schedule queue module exceeding a second threshold.

6. The microprocessor of claim 5 , wherein the second threshold is lower than the first threshold.

7. The microprocessor of claim 5 , wherein the stall condition comprises a second level cache miss for one of the stored second decoded instructions.

8. The microprocessor of claim 5 , wherein the schedule queue module is configured to flush the stored first decoded instructions also in response to (i) the count of the stored first decoded instructions exceeding a third threshold (ii) for longer than a predetermined time.

9. The microprocessor of claim 1 , wherein the schedule queue module is configured to flush the stored first decoded instructions in response to (i) the count of the stored first decoded instructions exceeding a second threshold (ii) for longer than a predetermined time.

10. The microprocessor of claim 9 , further comprising a timer configured to track a time that the count of the stored first decoded instructions exceeds the second threshold.

11. The microprocessor of claim 1 , wherein the microprocessor is configured to execute a plurality of threads including the first thread, the second thread, and at least one additional thread.

12. The microprocessor of claim 1 , wherein the front end module is configured to, for selected ones of the first instructions, generate multiple first decoded instructions for each of the selected ones of the first instructions.

13. A method of operating a microprocessor, the method comprising:
retrieving first instructions, corresponding to a first thread, from an instruction cache;
retrieving second instructions, corresponding to a second thread, from the instruction cache;
decoding the first instructions into first decoded instructions;
decoding the second instructions into second decoded instructions;
selectively storing the first decoded instructions and the second decoded instructions in a schedule queue for future issuance, wherein the selectively storing includes rejecting storage of an additional one of the first decoded instructions in the schedule queue in response to a count of the stored first decoded instructions in the schedule queue exceeding a first threshold, wherein the first threshold is smaller than a total number of instructions that the schedule queue is capable of storing; and
for each stored decoded instruction, selectively issuing the stored decoded instruction from the schedule queue to an execution unit,
wherein the first threshold is based on a difference between (i) the total number of instructions and (ii) a total number of threads serviced by the schedule queue.

14. The method of claim 13 , wherein the selectively issuing includes, for each stored decoded instruction, issuing the stored decoded instruction to the execution unit in response to dependencies being resolved for the stored decoded instruction.

15. The method of claim 13 , further comprising flushing the stored first decoded instructions in response to both (i) the stored first decoded instructions experiencing a stall condition and (ii) the count of the stored first decoded instructions in the schedule queue exceeding a second threshold.

16. The method of claim 13 , further comprising flushing the stored first decoded instructions from the schedule queue in response to ( 1 ) the count of the stored first decoded instructions exceeding a second threshold (ii) for longer than a predetermined time.

17. The method of claim 15 , wherein the second threshold is lower than the first threshold.

18. The method of claim 15 , wherein the stall condition comprises a second level cache miss for one of the stored second decoded instructions.

19. The method of claim 15 , further comprising flushing the stored first decoded instructions also in response to (i) the count of the stored first decoded instructions exceeding a third threshold (ii) for longer than a predetermined time.

20. The method of claim 13 , further comprising generating, for selected ones of the first instructions, multiple first decoded instructions for each of the selected ones of the first instructions.

Assignees

• Marvell Int Ltd

Inventors

• Hameenanttila Tom
• O'Bleness R Frank
• Jamil Sujat
• Delgross Joseph

Classifications

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/5061

  Partitioning or combining of resources · CPC title

• G06F11/0754

  by exceeding limits · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title