Compiler method for generating instructions for vector operations on a multi-endian processor

Patent metadata

Field	Value
Publication number	US-9606780-B2
Application number	US-201414583674-A
Country	US
Kind code	B2
Filing date	Dec 27, 2014
Priority date	Dec 19, 2014
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias. The compiler uses a code generation endian preference that is specified by the user, and that determines a natural element order. When the compiler processes a computer program, it generates instructions for vector operations by determining whether the vector instruction has an endian bias that matches the specified endian preference. When the vector instruction has no endian bias, or when the endian bias of the vector instruction matches the specified endian preference, the compiler generates one or more instructions for the vector instruction as it normally does. When the endian bias of the vector instruction does not match the specified endian preference, the compiler generates instructions to fix the mismatch.

First claim

The invention claimed is:

1. An apparatus comprising:
at least one processor;
a memory coupled to the at least one processor;
a computer program residing in the memory, the computer program including a plurality of instructions;
an endian preference for the apparatus that defines a natural element order for vector instructions; and
a compiler residing in the memory and executed by the at least one processor, the compiler including a vector instruction processing mechanism that determines when a vector instruction has an inherent element order that is a mismatch to the natural element order, and in response, generates at least one instruction to fix the mismatch.

2. The apparatus of claim 1 wherein the vector processing mechanism determines when the vector instruction specifies a first element number, and in response, generates an instruction that references a second element number computed by subtracting the first element number from a number of elements in the vector minus one.

3. The apparatus of claim 1 wherein the vector processing mechanism determines when the vector instruction specifies odd elements, and in response, generates an instruction that specifies even elements, and determines when the vector instruction specifies even elements, and in response, generates an instruction that specifies odd elements.

4. The apparatus of claim 1 wherein the vector processing mechanism determines when the vector instruction is a vector load instruction, and in response, generates a vector element reverse instruction after the vector load instruction.

5. The apparatus of claim 1 wherein the vector processing mechanism determines when the vector instruction is a vector store instruction, and in response, generates a vector element reverse instruction before the vector store instruction.

6. The apparatus of claim 4 wherein each vector element reverse instruction reverses order of a plurality of elements of a vector register.

7. The apparatus of claim 6 wherein the plurality of elements of the vector register comprises one of:
a plurality of bytes;
a plurality of halfwords;
a plurality of words;
a plurality of double-words;
a plurality of quadwords; and
a plurality of elements larger than quadwords.

8. The apparatus of claim 1 wherein the vector processing mechanism determines when the vector instruction is an instruction that has input arguments treated as an extended vector, and in response, generates a vector instruction with an inverted order of the input arguments.

9. The apparatus of claim 1 wherein the vector processing mechanism determines when the vector instruction refers to a high half of at least one vector register, and in response, generates an instruction that refers to a low half of the at least one vector register, and determines when the vector instruction refers to a low half of at least one vector register, and in response, generates an instruction that refers to the high half of the at least one vector register.

Assignees

• IBM

Inventors

• Gschwind Michael Karl
• Ji Jin Song
• Schmidt William J

Classifications

• G06F8/445 Primary

  Exploiting fine grain parallelism, i.e. parallelism at instruction level (run-time instruction scheduling G06F9/3836) · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F8/41 Primary

  Compilation · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title