Energy efficient high-speed link and method to maximize energy savings on the energy efficient high-speed link

Patent metadata

Field	Value
Publication number	US-9606604-B1
Application number	US-201514951544-A
Country	US
Kind code	B1
Filing date	Nov 25, 2015
Priority date	Nov 25, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

In high-speed link structures a receiver outputs a signal detect indicator (SDI) with a first logic value when transmissions are detected and a second logic value when suspension of transmissions is detected. A controller detects transitions in the SDI and causes corresponding transitions in an energy detect indicator (EDI). A physical control sublayer (PCS) has different operating states that cause the receiver to operate in different power modes and transitions between the operating states based on the EDI. If the EDI has the second logic value, the PCS remains in a non-active state and the receiver operates in a low power idle (LPI) mode. When the EDI transitions to the first logic value, the PCS exits the non-active state and the receiver operates in a non-LPI mode. To ensure that the PCS properly enters and doesn't pre-maturely exit the non-active state, EDI transitions to the first logic value are delayed.

First claim

What is claimed is:

1. A structure comprising:
a receiver receiving data signals intermittently transmitted by a transmitter over a channel,
the receiver comprising a signal detector that detects data signal transmissions on the channel and suspension of the data signal transmissions, and
the signal detector outputting a signal detect indicator and causing the signal detect indicator to be a first logic value during the data signal transmissions and a second logic value during the suspension of the data signal transmissions; and,

a signal controller receiving the signal detect indicator and outputting an energy detect indicator,
the signal controller further detecting transitions in the signal detect indicator and causing corresponding transitions in the energy detect indicator such that any transition of the energy detect indicator from the second logic value to the first logic value is delayed.

2. The structure of claim 1 , the transition of the energy detect indicator from the second logic value to the first logic value being delayed until a predetermined time period has elapsed.

3. The structure of claim 2 , the predetermined time period being adjustable.

4. The structure of claim 1 , further comprising a physical control sublayer causing operation in a normal power mode when the energy detect indicator has the first logic value and remaining in a low power idle mode when the energy detect indicator has the second logic value.

5. The structure of claim 1 , the first logic value being a “1” value and the second logic value being a “0” value.

6. The structure of claim 1 , the receiver entering a non-active state upon detecting the suspension of the data signal transmissions by the transmitter and the receiver exiting the non-active state upon detecting resumption of the data signal transmissions by the transmitter.

7. The structure of claim 6 , further comprising a system interrupt controller, the signal controller further outputting an interrupt control signal to the system interrupt controller,
when the receiver is in the non-active state, the signal controller holding the interrupt control signal at the first logic value, and
when the receiver has exited the non-active state, the signal controller permitting the interrupt control signal to transition in response to transitions detected in the signal detect indicator subject to a delay of a predetermined time period.

8. The structure of claim 1 , the channel comprising a high-speed serial link.

9. A structure comprising:
a receiver receiving data signals intermittently transmitted by a transmitter over a channel,
the receiver comprising a signal detector that detects data signal transmissions on the channel and suspension of the data signal transmissions, and
the signal detector outputting a signal detect indicator and causing the signal detect indicator to be a first logic value during the data signal transmissions and a second logic value during the suspension of the data signal transmissions; and,

a signal controller receiving the signal detect indicator, evaluating signal detect indicator logic value stability, and outputting an energy detect indicator,
the signal controller further detecting transitions in the signal detect indicator and causing corresponding transitions in the energy detect indicator such that any transition of the energy detect indicator from the second logic value to the first logic value is delayed until either a predetermined time period has elapsed or a stable signal detect indicator first logic value is detected.

10. The structure of claim 9 , the predetermined time period being adjustable.

11. The structure of claim 9 , further comprising a physical control sublayer causing operation in a normal power mode when the energy detect indicator has the first logic value and remaining in a low power idle mode when the energy detect indicator has the second logic value.

12. The structure of claim 9 , the receiver entering a non-active state upon detecting the suspension of the data signal transmissions by the transmitter and the receiver exiting the non-active state upon detecting resumption of the data signal transmissions by the transmitter.

13. The structure of claim 12 , further comprising a system interrupt controller, the signal controller further outputting an interrupt control signal to the system interrupt controller,
when the receiver is in the non-active state, the signal controller holding the interrupt control signal at the first logic value, and
when the receiver has exited the non-active state, the signal controller permitting the interrupt control signal to transition in response to transitions detected in the signal detect indicator subject to a delay of the predetermined time period.

14. A method comprising:
receiving, by a receiver, data signals intermittently transmitted by a transmitter over a channel;
detecting, by the receiver, data signal transmissions on the channel and suspension of the data signal transmissions;
outputting, by the receiver, a signal detect indicator having a first logic value during the data signal transmissions and a second logic value during the suspension of the data signal transmissions;
receiving, by a signal controller operably connected to the receiver, the signal detect indicator;
detecting, by the signal controller, transitions in the signal detect indicator; and,
outputting, by the signal controller to a physical control sublayer, an energy detect signal with corresponding transitions such that any transition of the energy detect indicator from the second logic value to the first logic value is delayed.

15. The method of claim 14 , the transition of the energy detect indicator from the second logic value to the first logic value being delayed until a predetermined time period has elapsed.

16. The method of claim 15 , the predetermined time period being adjustable.

17. The method of claim 14 , further comprising evaluating, by the signal controller, signal detect indicator logic value stability, the transition of the energy detect indicator from the second logic value to the first logic value being delayed until either a predetermined time period has elapsed or a stable signal detect indicator first logic value is detected.

18. The method of claim 14 , further comprising causing, by the physical control sublayer, operation in a normal power mode when the energy detect indicator has the first logic value and remaining in a low power idle mode when the energy detect indicator has the second logic value.

19. The method of claim 14 , further comprising entering a non-active state upon detecting the suspension of the data signal transmissions and exiting the non-active state upon detecting resumption of the data signal transmissions.

20. The method of claim 19 , further comprising:
outputting, by the signal controller to a system interrupt controller, an interrupt control signal,
the interrupt control signal being held at the first logic value, when the receiver is in the non-active state,
the interrupt control signal being permitted to transition in response to transitions detected in the signal detect indicator subject to a delay of a predetermined time period, when the receiver has exited the non-active state.

Assignees

• Globalfoundries Inc

Inventors

• Butter Adrian S

Classifications

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3209 Primary

  Monitoring remote activity, e.g. over telephone lines or network connections · CPC title