Electronic device and method for maintaining functionality of an integrated circuit during electrical aggressions

Patent metadata

Field	Value
Publication number	US-9606159-B2
Application number	US-201214394792-A
Country	US
Kind code	B2
Filing date	Apr 26, 2012
Priority date	Apr 26, 2012
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed.

First claim

The invention claimed is:

1. An electronic device, comprising:
a band gap circuit configured to receive a supply voltage and to output a reference voltage having a voltage relative to a ground voltage;
a reference current circuit coupled to the band gap circuit to receive the reference voltage and configured to generate a reference current;
a first filter connected between the band gap circuit and the reference current circuit and configured to filter out variations of the reference voltage;
a voltage regulator coupled to the band gap circuit to receive the reference voltage and configured to generate a supply voltage;
a second filter connected between the band gap circuit and the voltage regulator;
a detection circuit configured to generate a detection signal in response to an electrostatic discharge perturbation, the detection signal correlating in time with the electrostatic discharge perturbation;
a clock coupled to the reference current circuit to receive the reference current and coupled to the voltage regulator to receive the supply voltage, and configured to generate a clock signal having a clock period;
a deglitcher circuit; and
a protection circuit including the deglitcher circuit and coupled to the clock to receive the clock signal, and configured to generate an error signal in response to the detection signal only when a duration of the detection signal exceeds a predefined multiple of the clock period, wherein the deglitcher circuit filters said detection signal and wherein the multiple is less than 1.

2. The device of claim 1 , wherein the detection signal is a power-on reset (POR) signal, an over voltage signal, or an under voltage signal.

3. The device of claim 1 , further comprising a third filter coupled to the protection circuit to filter the error signal.

4. The device of claim 1 , wherein the voltage regulator comprises an analog voltage regulator configured to provide an analog reference voltage to the clock.

5. The device of claim 1 , wherein the voltage regulator comprises a digital voltage regulator configured to provide a digital reference voltage to the clock.

6. The device of claim 1 , wherein the multiple of said clock period is between 0.2 and 0.5 clock periods.

7. The device of claim 1 , wherein the multiple of said clock period is between 0.1 and 1.0 microseconds.

8. The device of claim 1 , comprising an output stage connected to the protection circuit and responsive to the error signal.

9. The device of claim 8 , wherein the output stage comprises a power switch.

10. A method for protecting electronic circuitry, comprising:
filtering a reference voltage with a set of filters to provide a filtered reference voltage;
generating a reference current with the filtered reference voltage at a reference current unit;
generating a supply voltage with the filtered reference voltage at a voltage regulator;
generating a detection signal in response to an electrostatic discharge perturbation, the detection signal correlating in time with the electrostatic discharge perturbation;
operating a clock with the supply voltage and the reference current;
generating a clock signal having a clock period with the clock;
generating an error signal in response to the detection signal only when a duration of the detection signal exceeds a predefined multiple of said clock period, wherein the multiple is less than 1.

11. The method of claim 10 , wherein the detection signal is a power-on reset (POR) signal, an over voltage signal, or an under voltage signal.

12. The method of claim 10 , further comprising filtering the error signal with a third filter.

13. The method of claim 10 , wherein the multiple of the clock period is between 0.2 and 0.5 clock periods.

14. The method of claim 10 , wherein the multiple of the clock period is between 0.1 and 1.0 microseconds.

15. An electronic device, comprising:
a set of filters including a first filter, a second filter, and a third filter;
a reference current circuit coupled to receive a first reference voltage and configured to generate a reference current, wherein the first filter filters the first reference voltage to provide a filtered first reference voltage to the reference current unit;
a voltage regulator coupled to receive a second reference voltage and configured to generate a supply voltage, wherein the second filter filters the second reference voltage to provide a filtered second reference voltage to the voltage regulator;
a detection circuit configured to generate a detection signal in response to an electrostatic discharge perturbation, the detection signal correlating in time with the electrostatic discharge perturbation;
a clock coupled to the reference current circuit to receive the reference current and coupled to the voltage regulator to receive the supply voltage, and configured to generate a clock signal having a clock period;
a deglitcher circuit;
a protection circuit including the deglitcher circuit and coupled to the clock to receive the clock signal, and configured to generate an error signal in response to the detection signal only when a duration of the detection signal exceeds a predefined multiple of said clock period, wherein the deglitcher circuit filters said detection signal and wherein the multiple is less than 1; and
a power switch coupled to said protection circuit to receive the error signal and responsive to said error signal, wherein the third filter is connected between the protection circuit and the power switch to filter the error signal.

16. The device of claim 15 , wherein the detection signal is a power-on reset (POR) signal, an over voltage signal, or an under voltage signal.

17. The device of claim 15 , wherein the voltage regulator comprises an analog voltage regulator configured to provide an analog reference voltage to the clock.

18. The device of claim 15 , wherein the voltage regulator comprises a digital voltage regulator configured to provide a digital reference voltage to the clock.

19. The device of claim 15 , wherein the first filter is a low pass filter.

20. The device of claim 15 , wherein the second filter is a low pass filter.

21. An electronic device, comprising:
a band gap circuit configured to receive a supply voltage and to output a reference voltage having a voltage relative to a ground voltage;
a reference current circuit coupled to the band gap circuit to receive the reference voltage and configured to generate a reference current;
a first filter connected between the band gap circuit and the reference current circuit and configured to filter out variations of the reference voltage;
a voltage regulator coupled to the band gap circuit to receive the reference voltage and configured to generate a supply voltage;
a second filter connected between the band gap circuit and the voltage regulator;
a detection circuit configured to generate a detection signal in response to an electrostatic discharge perturbation, the detection signal correlating in time with the electrostatic discharge perturbation;
a clock coupled to the reference current circuit to receive the reference current and coupled to the voltage regulator to receive the supply voltage, and configured to generate a clock signal having a clock period;
a deglitcher circuit; and
a protection circuit including the deglitcher circuit and coupled to the clock to receive the clock signal, and configured to generate an error signal in response to the detection signal only when a duration of the detecti

Assignees

• Besse Patrice
• Bernon-Enjalbert Valérie
• Givelin Philippe
• Nxp Usa Inc

Inventors

• Besse Patrice
• Bernon-Enjalbert Valérie
• Givelin Philippe

Classifications

• G01R31/002 Primary

  where the device under test is an electronic circuit · CPC title

• H01L27/0251

  Electricity · mapped topic

• H03K17/08122 Primary

  in field-effect transistor switches · CPC title

• H03K17/0822

  in field-effect transistor switches · CPC title

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title