Electronic package with narrow-factor via including finish layer

Patent metadata

Field	Value
Publication number	US-9603247-B2
Application number	US-201414456606-A
Country	US
Kind code	B2
Filing date	Aug 11, 2014
Priority date	Aug 11, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

This disclosure relates generally to an electronic package and methods that include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via. The via may be formed within the package insulator layer and electrically coupled to the electrically conductive pad. The via may include a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.

First claim

What is claimed is:

1. An electronic package, comprising:
an electrically conductive pad;
a first package insulator layer including a substantially non-conductive material; and
a first via, formed within the package insulator layer, electrically coupled to a front side of the electrically conductive pad, the first via comprising:
a nickel conductor extending vertically through at least part of the package insulator layer and having a first end coupled to the electrically conductive pad and a second end opposite the first end;
a finish layer coupled to the second end of the conductor, the finish layer including a gold compound
an embedded bridge within the electronic package;
a second package insulator layer between a backside of the electrically conductive pad and the embedded bridge; and
a copper via formed through the second package insulator layer, and coupled between the backside of the electrically conductive pad and the embedded bridge.

2. The electronic package of claim 1 , wherein the gold compound is a palladium-gold compound.

3. The electronic package of claim 1 , wherein the gold compound is one of electroless nickel immersion gold (ENIG), ENIG plus electroless gold (ENIG+EG), and Nickel-Palladium-Gold (NiPdAu).

4. The electronic package of claim 1 , wherein the first package insulator layer comprises at least one of a buildup dielectric material and a solder resist.

5. The electronic package of claim 4 , wherein the buildup dielectric material is an Ajinomoto buildup film.

6. The electronic package of claim 1 , wherein the first package insulator layer encloses, at least in part, the electrically conductive pad.

7. The electronic package of claim 1 , further comprising a solder ball coupled to the finish layer.

8. The electronic package of claim 7 , wherein the solder is configured to be electrically coupled to a connector of a silicon die.

9. The electronic package of claim 1 , wherein the embedded bridge is a silicon bridge.

10. A method of making an electronic package, comprising:
forming an electrically conductive pad;
forming a first package insulator layer including a substantially non-conductive material;
forming a first nickel via extending vertically through at least part of the first package insulator layer and having a first end coupled to the electrically conductive pad and a second end opposite the first end; and
coupling a finish layer to the second end of the first nickel via, the finish layer including a gold compound;
embedding a bridge within the electronic package;
forming a second package insulator layer between a backside of the electrically conductive pad and the bridge; and
forming a copper via through the second package insulator layer, and coupled between the backside of the electrically conductive pad and the bridge.

11. The method of claim 10 , wherein the gold compound is a palladium-gold compound.

12. The method of claim 10 , wherein the gold compound is one of electroless nickel immersion gold (ENIG), ENIG plus electroless gold (ENIG+EG), and Nickel-Palladium-Gold (NiPdAu).

13. The method of claim 10 , wherein the first package insulator layer comprises at least one of a buildup dielectric material and a solder resist.

14. The method of claim 13 , wherein the buildup dielectric material is an Ajinomoto buildup film.

15. The method of claim 10 , wherein the first package insulator layer encloses, at least in part, the electrically conductive pad.

16. The method of claim 10 , further comprising coupling a solder ball to the finish layer.

17. The method of claim 16 , wherein the solder is configured to be electrically coupled to a connector of a silicon die.

18. The method of claim 10 , wherein embedding the bridge includes embedding a silicon bridge.

Assignees

• Intel Corp

Inventors

• Swaminathan Rajasekaran
• Agraharam Sairam
• Alur Amruthavalli Pallavi
• Viswanath Ram
• Jen Wei-Lun Kane

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title