Jack detector and jack detecting method

Patent metadata

Field	Value
Publication number	US-9602941-B2
Application number	US-201414174394-A
Country	US
Kind code	B2
Filing date	Feb 6, 2014
Priority date	Feb 13, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A jack detector detects a combination state between a socket including a detecting pin and a first signal pin and a jack. The jack detector includes a first current source for supplying a first detecting current, a second current source for supplying a second detecting current larger than the first detecting current, and a buffer for generating a detecting signal in accordance with a detecting pin voltage input from the detecting pin. The second current source instead of the first current source is connected to the detecting pin in synchronization with a combination starting point when the detecting pin and the first signal pin are electrically connected to each other and it is determined that the jack is combined with the socket when the detecting signal is maintained at a state of the combination starting point.

First claim

What is claimed is:

1. A jack detector for detecting a combination state between a jack and an audio socket, the audio socket including a detecting pin and a first signal pin, the jack detector comprising:
a first current source and configured to selectively supply a first detecting current to the detecting pin;
a second current source configured to selectively supply a second detecting current larger than the first detecting current to the detecting pin; and
a buffer coupled to the detecting pin and configured to generate a detecting signal in accordance with a detecting pin voltage input from the detecting pin,
the jack detector operable to determine that the jack is combined with the audio socket when a difference between the detecting signal at a combination starting point when the detecting pin and the first signal pin are electrically connected to each other and the first detecting current is supplied to the detecting pin, and the detecting signal after the second detecting current is supplied to the detecting pin in synchronization with the combination starting point, is smaller than a predetermined reference voltage.

2. The jack detector of claim 1 , further comprising:
a first switch connected between the first current source and the detecting pin;
a second switch connected between the second current source and the detecting pin;
wherein the first switch is operable to be turned on and the second switch is operable to be turned off at least until the combination starting point is detected; and
wherein the first switch is operable to be turned off and the second switch is operable to be turned on after a predetermined delay from the combination starting point.

3. The jack detector of claim 1 , wherein the buffer is operable to generate a first level detecting signal when the detecting pin voltage is larger than the predetermined reference voltage and is operable to generate a second level detecting signal when the detecting voltage is smaller than the reference voltage.

4. The jack detector of claim 1 , further comprising
a controller configured to sense the combination starting point using the detecting signal and to control a connection between the first current source and the detecting pin and a connection between the second current source and the detecting pin in synchronization with the combination starting point.

5. The jack detector of claim 4 , wherein the controller senses a point in time when the detecting signal is changed from a first level to a second level as the combination starting point and generates an enable signal when the detecting signal is maintained at the second level after the combination starting point.

6. The jack detector of claim 5 , further comprising:
a first switch connected between the first current source and the detecting pin; and
a second switch connected between the second current source and the detecting pin.

7. The jack detector of claim 6 , wherein the controller generates a first switch signal at a level where the first switch is turned on and a second switch signal at a level where the second switch is turned off until at least the combination starting point and generates the first switch signal at a level where the first switch is turned off and the second switch signal at a level where the second switch is turned on after a predetermined delay from the combination starting point.

8. The jack detector of claim 5 , wherein a signal is supplied to the first receiving pin in accordance with the enable signal.

9. The jack detector of claim 1 , wherein the jack comprises a terminal connected to the detecting pin and the first receiving pin when the jack is combined with the audio socket.

10. A method of detecting a combination state between an audio socket including a detecting pin and a first signal pin and a jack, the method comprising:
supplying a first detecting current to the detecting pin;
generating a detecting signal in accordance with a detecting pin voltage input from the detecting pin;
supplying a second detecting current larger than the first detecting current to the detecting pin instead of the first detecting current in synchronization with a combination starting point when the detecting pin and the first signal pin are electrically connect to each other; and
determining that the jack is combined with the audio socket when the detecting signal is maintained at a state of the combination starting point at a point in time when the detecting signal is detected after the second detecting current is supplied to the detecting pin.

11. The method of claim 10 , wherein:
generating the detecting signal comprises:
generating a first level detecting signal when the detecting pin voltage is larger than a predetermined reference voltage; and
generating a second level detecting signal when the detecting voltage is smaller than the reference voltage.

12. The method of claim 11 , further comprising:
sensing a point in time when the detecting signal is changed from a first level to a second level as the combination starting point.

13. The method of claim 10 , further comprising:
generating the enable signal when it is determined that the jack is combined with the audio socket.

14. The method of claim 13 , further comprising:
supplying a signal to the first receiving pin in accordance with the enable signal.

15. The method of claim 10 , wherein the jack comprises a terminal connected to the detecting pin and the first receiving pin when the jack is combined with the audio socket.

16. A detection device comprising:
a detection circuit configured to selectively apply a first current to a detecting pin of an audio socket and to selectively apply a second current to the detecting pin of an audio socket according to a voltage of the detecting pin generated from the first current; and
a level circuit configured to generate levels that correspond to voltages of the detecting pin generated from the first current and the second current,
wherein it is determined whether a detection object is a jack or not according to a result of a comparison between the level generated at the detecting pin from to the first current and the level generated at the detecting pin from the second current.

17. The detection device of claim 16 , wherein the detection circuit comprises:
a first current source configured to supply the first current,
a second current source configured to supply the second current,
a first switch connected between the first current source and the terminal, and
a second switch connected between the second current source and the terminal, and
the first switch is controlled to be turned on and the second switch is controlled to be turned off until before the detection object touches a terminal coupled to the detecting pin and the first switch is controlled to be turned off and the second switch is controlled to be turned on after the detection object touches the terminal.

18. The detection device of claim 16 , wherein the level circuit is configured to generate a first level when the voltage of the detecting pin is higher than a reference voltage and to generate a second level when the voltage of the detecting pin is lower than the reference voltage.

19. The detection device of claim 18 , wherein, when an output of the level circuit is maintained with the second level after the output is changed to the second level from the first level, the detection object is determined to be a jack.

20. The detection device of claim 16 , wherein the detec

Assignees

• Fairchild Korea Semiconductor Ltd
• Fairchild Korea Semiconductor Ltd

Inventors

• Oh Jae Young
• Lee Hyung Seok

Classifications

• H04R5/04

  Circuit arrangements, {e.g. for selective connection of amplifier inputs/outputs to loudspeakers, for loudspeaker detection, or for adaptation of settings to personal preferences or hearing impairments (combinations of amplifiers H03F3/68; stereophonic systems H04S)} · CPC title

• H04R29/004 Primary

  for microphones (H04R29/007 takes precedence) · CPC title

• G01R27/08

  Measuring resistance by measuring both voltage and current · CPC title

• H02B1/00

  Frameworks, boards, panels, desks, casings; Details of substations or switching arrangements · CPC title

• H04R2420/05

  Detection of connection of loudspeakers or headphones to amplifiers · CPC title