Technologies for high-speed PCS supporting FEC block synchronization with alignment markers

Patent metadata

Field	Value
Publication number	US-9602401-B2
Application number	US-201414580737-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Sep 22, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Technologies for high-speed data transmission include a network port logic having one or more communication lanes coupled to a forward error correction (FEC) sublayer and a physical coding sublayer (PCS). To transmit data, the PCS encodes the data to be transmitted into encoded data blocks using a 66 b/64 b line code and inserts alignment marker blocks after every 16,383 encoded data blocks. The FEC encodes the encoded data blocks into 80-block FEC codewords starting at a predefined offset from an alignment marker. Thus, each alignment marker is at one of five predefined offsets from the beginning of an FEC codeword. Each alignment marker may include a unique block type field usable with FEC encoding. The PCS may include one or more logical lanes, each operating at 25 Gb/s. Embodiments of the network port logic may include a single PCS lane or sixteen PCS lanes. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. A network interface circuit for high-speed data transmission, the network interface circuit comprising network port logic including:
a physical coding sublayer (PCS) logic to (i) encode first data to be transmitted into first encoded data blocks using a 66 b/64 b line code; and (ii) insert an alignment marker block into the first encoded data blocks after every first integer number of encoded data blocks to generate first aligned data blocks at a first PCS lane speed; and
a forward error correction (FEC) logic to encode the first aligned data blocks into first FEC codewords that each start at a predefined offset from an alignment marker block of the first aligned data blocks, wherein each of the first FEC codewords includes a second number of aligned data blocks and wherein the first integer number of encoded data blocks plus one and the second number of aligned data blocks have a greatest common divisor greater than one.

2. The network interface circuit of claim 1 , wherein the first PCS lane speed comprises 25 gigabits per second.

3. The network interface circuit of claim 1 , wherein the first PCS lane speed comprises 50 gigabits per second.

4. The network interface circuit of claim 1 , wherein to encode the first aligned data blocks further comprises to:
transcode the first aligned data blocks to generate first transcoded data blocks using a 257 b/256 b transcoding algorithm; and
encode the first transcoded data blocks into the first FEC codewords that each start at the predefined offset from an alignment marker block of the first transcoded data blocks.

5. The network interface circuit of claim 4 , wherein the alignment marker block comprises a data block with predetermined content, wherein the unique block type field comprises a binary value corresponding to hexadecimal 0x33.

6. The network interface circuit of claim 1 , wherein the first integer number of encoded data blocks comprises 20,479 encoded data blocks, and the second number of aligned data blocks comprises 80 aligned data blocks.

7. The network interface circuit of claim 1 , wherein:
the PCS logic is further to distribute the first encoded data blocks onto a plurality of PCS lanes of the PCS logic, wherein each PCS lane operates at the PCS lane speed;
to insert the alignment marker block comprises to insert, for each PCS lane, a corresponding alignment marker block into the first encoded data blocks after every first integer number of encoded data blocks distributed on the corresponding PCS lane to generate the first aligned data blocks for the corresponding PCS lane; and
to encode the first aligned data blocks into first FEC codewords that each start at the predefined offset from an alignment marker block of the first aligned data blocks comprises to encode, for each PCS lane, the first aligned data blocks for the corresponding PCS lane into first FEC codewords that each start at the predefined offset from an alignment marker block of the first aligned data blocks for the corresponding PCS lane.

8. A network interface circuit for high-speed data transmission, the network interface circuit comprising network port logic including:
a physical coding sublayer (PCS) logic to (i) encode first data to be transmitted into first encoded data blocks using a 66 b/64 b line code, (ii) insert an alignment marker block into the first encoded data blocks after every first integer number of encoded data blocks to generate first aligned data blocks at a first PCS lane speed, and (iii) distribute the first encoded data blocks onto a plurality of PCS lanes of the PCS logic, wherein each PCS lane operates at the PCS lane speed; and
a forward error correction (FEC) logic to encode the first aligned data blocks into first FEC codewords and stripe the first FEC codewords onto a plurality of PMA lanes;
wherein to insert the alignment marker block comprises to insert, for each PCS lane, an alignment marker block into the first encoded data blocks after every first integer number of encoded data blocks distributed on the corresponding PCS lane to generate the first aligned data blocks for the corresponding PCS lane.

9. The network interface circuit of claim 8 , wherein to encode the first aligned data blocks into the first FEC codewords comprises to:
align the PCS lanes to generate an encoded data stream that includes the aligned data blocks;
extract, for each of the PCS lanes, the corresponding alignment marker block from the encoded data stream at a corresponding original position in the encoded data stream;
transcode, after extraction of the alignment marker blocks, the encoded data stream to generate first transcoded data blocks using a 257 b/256 b transcoding algorithm;
encode the first transcoded data blocks into the first FEC codewords; and
re-insert, for each of the PCS lanes, the corresponding alignment marker block into a corresponding PMA lane after an end of a first FEC codeword in response to striping of the first FEC codewords onto the plurality of PMA lanes, wherein the first FEC codeword includes the corresponding original position in the encoded data stream.

10. A method for high-speed data transmission, the method comprising:
encoding, by a physical coding sublayer (PCS) logic of a network port logic, first data to be transmitted into first encoded data blocks using a 66 b/64 b line code;
inserting, by the PCS logic of the network port logic, an alignment marker block into the first encoded data blocks after every first integer number of encoded data blocks to generate first aligned data blocks at a first PCS lane speed; and
encoding, by a forward error correction (FEC) logic of the network port logic, the first aligned data blocks into first FEC codewords that each start at a predefined offset from an alignment marker block of the first aligned data blocks, wherein each of the first FEC codewords includes a second number of aligned data blocks and wherein the first integer number of encoded data blocks plus one and the second number of aligned data blocks have a greatest common divisor greater than on.

11. The method of claim 10 , further comprising:
distributing, by the PCS logic of the network port logic, the first encoded data blocks onto a plurality of PCS lanes of the PCS logic, wherein each PCS lane operates at the PCS lane speed;
wherein inserting the alignment marker block comprises inserting, for each PCS lane, a corresponding alignment marker block into the first encoded data blocks after every first integer number of encoded data blocks distributed on the corresponding PCS lane to generate the first aligned data blocks for the corresponding PCS lane; and
wherein encoding the first aligned data blocks into first FEC codewords that each start at the predefined offset from an alignment marker block of the first aligned data blocks comprises encoding, for each PCS lane, the first aligned data blocks for the corresponding PCS lane into first FEC codewords that each start at the predefined offset from an alignment marker block of the first aligned data blocks for the corresponding PCS lane.

12. A method for high-speed data transmission, the method comprising:
encoding, by a physical coding sublayer (PCS) logic of a network port logic, first data to be transmitted into first encoded data blocks using a 66 b/64 b line code;
inserting, by the PCS logic of the network port logic, an alignment marker block into the first encoded data blocks after every first integer number of encoded data blocks to generate first aligned data blocks at a first PCS lane speed;
distributing, by the PCS logic of the network port logic, the first encoded data blocks onto a plurality of PCS

Assignees

• Intel Corp

Inventors

• Ran Adee O
• Lusted Kent C

Classifications

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• H04L45/66 Primary

  Layer 2 routing, e.g. in Ethernet based MAN's · CPC title

• H03M13/25

  Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] {(modulation codes H03M13/31)} · CPC title

• H04L1/0041 Primary

  Arrangements at the transmitter end · CPC title

• H03M13/251

  with block coding · CPC title