Method and apparatus for passive continuous-time linear equalization with continuous-time baseline wander correction

Patent metadata

Field	Value
Publication number	US-9602315-B2
Application number	US-201414569574-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Dec 12, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Described is an apparatus which comprises: an amplifier; and a passive continuous-time linear equalizer integrated with a baseline wander (BLW) corrector, wherein the integrated equalizer and BLW corrector is coupled to the amplifier.

First claim

We claim:

1. An apparatus comprising:
a differential amplifier; and
an equalizer integrated within a baseline wander (BLW) corrector such that the equalizer and the BLW corrector comprise common circuits, wherein the equalizer integrated within the BLW corrector is coupled to the differential amplifier, wherein the differential amplifier is to receive inputs from the equalizer integrated within the BLW corrector, and wherein the BLW corrector is a continuous-time BLW corrector.

2. The apparatus of claim 1 , wherein the equalizer is a passive continuous-time linear equalizer.

3. The apparatus of claim 1 comprises a reference voltage provider to provide a common mode reference voltage to the differential amplifier input via the BLW corrector.

4. The apparatus of claim 1 , wherein the equalizer comprises a high frequency path coupled to an input of a receiver and to the differential amplifier.

5. The apparatus of claim 4 , wherein the high frequency path comprises:
a first capacitive device coupled to the input of the receiver and to the differential amplifier;
a second capacitive device; and
a resistive device coupled to the amplifier and to the second capacitive device.

6. The apparatus of claim 5 , wherein the resistive device has programmable resistance.

7. The apparatus of claim 5 , wherein the second capacitive device has programmable capacitance.

8. The apparatus of claim 4 , wherein the BLW corrector comprises a low frequency path coupled to the input of the receiver and to the differential amplifier.

9. The apparatus of claim 4 , wherein the high frequency path is a differential path.

10. The apparatus of claim 8 , wherein the low frequency path is a differential path.

11. The apparatus of claim 8 , wherein the low frequency path comprises one or more resistive devices coupled to the input of the receiver and to the differential amplifier.

12. The apparatus of claim 1 further comprises a decision feedback equalizer coupled to an output of the differential amplifier.

13. The apparatus of claim 1 further comprises a ground referenced termination impedance coupled to the equalizer integrated within the BLW corrector.

14. The apparatus of claim 1 , wherein the equalizer applies adjustable capacitance ratio to realize linear equalization with AC-to-DC peaking.

15. The apparatus of claim 14 , wherein the equalizer integrated within the BLW corrector is configured to decouple a stable peaking frequency from the AC-to-DC peaking.

16. The apparatus of claim 1 , wherein the equalizer integrated within the BLW corrector is at least part of one of:
PCI compliant receiver;
SATA compliant receiver; or
USB compliant receiver.

17. The apparatus of claim 1 , wherein the equalizer integrated within the BLW corrector comprises passive devices or transistors configured as resistors and capacitors.

18. An apparatus comprising:
a first pad;
a second pad;
a differential equalizer integrated within a differential baseline wander (BLW) corrector such that the differential equalizer integrated within the differential BLW corrector comprises common circuits, wherein the differential equalizer integrated within the differential BLW corrector is coupled to the first and second pads; and
a differential amplifier coupled to the differential equalizer integrated within the differential BLW corrector, wherein the differential amplifier is to receive inputs from the differential equalizer integrated within the differential BLW corrector, and wherein the differential BLW corrector is a continuous-time differential BLW corrector.

19. The apparatus of claim 18 comprises a reference voltage provider to provide a common mode reference voltage to the differential BLW corrector.

20. The apparatus of claim 18 , wherein the differential equalizer comprises a high frequency path, and wherein the differential BLW corrector comprises a low frequency path.

21. A system comprising:
a memory;
a processor coupled to the memory, the processor having a receiver including:
a differential amplifier; and
an equalizer integrated within a baseline wander (BLW) corrector such that the equalizer integrated within the BLW corrector comprises common circuits, wherein the equalizer integrated within the BLW corrector is coupled to the differential amplifier, wherein the differential amplifier is to receive inputs from the equalizer integrated within the BLW corrector, and wherein the BLW corrector is a continuous-time BLW corrector; and

a wireless interface for allowing the processor to communicate with another device.

22. The system of claim 21 , wherein the processor comprises a reference voltage provider to provide a common mode reference voltage to the BLW corrector.

23. The system of claim 21 , wherein the equalizer comprises a high frequency path coupled to an input of a receiver and to the differential amplifier.

Assignees

• Intel Corp

Inventors

• Islam Syed S
• Ho Yick Yaw
• Swartz Ronald W

Classifications

• H04L25/06

  DC level restoring means; Bias distortion correction {; Decision circuits providing symbol by symbol detection} · CPC title

• H04L25/03254

  Operation with other circuitry for removing intersymbol interference · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04L25/10

  Compensating for variations in line balance · CPC title