System and method for reconfigurable phase shifter and mixer

Patent metadata

Field	Value
Publication number	US-9602054-B2
Application number	US-201514930210-A
Country	US
Kind code	B2
Filing date	Nov 2, 2015
Priority date	Jul 15, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An analog circuit for generating a periodic signal at a selected phase, including one or more phase interpolators that receive orthogonal differential RF signals and a pair of differential gain signals. The differential in-phase RF signal is applied at respective gates of tail transistors, and a first differential gain signal is applied across gates of a transistor pair coupled to each of the tail transistors. The quadrature-phase RF signal and a second differential gain signal is similarly applied to another quad of transistors (i.e., pair of transistor pairs) and associated tail transistors. A load connected to the one transistor in each pair receives the output signal, at a phase corresponding to a ratio of the first and second gain signals. The gain signals may be DC or AC, which allows configuration of the circuit as a phase shifter or an upconversion mixer, and the load may be presented by a transform in which the phase also depends on the relative coupling from the in-phase and quadrature-phase sides of the phase interpolator.

First claim

What is claimed is:

1. An analog circuit for generating a periodic signal, comprising:
oscillator circuitry for generating first and second periodic differential signals at a first frequency and at a selected phase angle relative to one another;
at least one phase interpolator, having inputs receiving the first and second periodic differential signals, and having inputs receiving first and second differential gain signals, for generating a combined periodic signal having a frequency component corresponding to the first frequency and at a phase angle corresponding to a relationship of the first and second differential gain signals, wherein the at least one phase interpolator comprises:
a load;
a plurality of transistor pairs, each comprising first and second transistors, each having a conduction path and a gate, a first end of the conduction path of each of the first and second transistors connected at a common node, a second end of the conduction path of the first transistor coupled to the load, and a second end of the conduction path of the second transistor coupled to a bias voltage; and
a plurality of tail transistors, each associated with one of the transistor pairs, and each having a conduction path and a gate, a first end of the conduction path coupled to the common node of an associated one of the plurality of transistor pairs, a second end of the conduction path coupled to a reference voltage;

wherein the first differential gain signal is applied across the gates of the first and second transistors in first and second ones of the transistor pairs;
wherein the second differential gain signal is applied across the gates of the first and second transistors in each of third and fourth ones of the transistor pairs;
wherein the first periodic differential signal is applied across the gates of a first tail transistor associated with the first transistor pair, and of a second tail transistor associated with the second transistor pair;
and wherein the second periodic differential signal is applied across the gates of a third tail transistor associated with the third transistor pair, and of a fourth tail transistor associated with the fourth transistor pair.

2. The circuit of claim 1 , further comprising:
a plurality of digital-to-analog converters for generating the first and second differential gain signals responsive to digital data.

3. The circuit of claim 2 , wherein the first and second differential gain signals are DC differential voltages.

4. The circuit of claim 3 , wherein the selected phase angle of the first and second periodic differential signals is 90°.

5. The circuit of claim 4 , wherein the phase angle of the combined periodic signal corresponds to the inverse tangent of a ratio of the second differential gain signal to the first differential gain signal;
and wherein the combined periodic signal is at the first frequency.

6. The circuit of claim 3 , wherein the signal applied at the gate of the first tail transistor is at a phase angle of 180° from the signal applied at the gate of the second tail transistor;
and wherein the signal applied at the gate of the third tail transistor is at a phase angle of 180° from the signal applied at the gate of fourth second tail transistor.

7. The circuit of claim 2 , wherein each of the plurality of digital-to-analog converters comprises:
a first conducting leg comprising a first transistor and a plurality of resistors of substantially the same resistance value, the resistors connected in series with one another and with the conduction path of the first transistor between a power supply voltage and a ground voltage, where nodes between adjacent resistors correspond to tap points; and
a second conducting leg comprising a second transistor and a plurality of resistors of substantially the same resistance value, the resistors connected in series with one another and with the conduction path of the second transistor between a power supply voltage and a ground voltage, where nodes between adjacent resistors correspond to tap points;
wherein a control terminal of the first transistor receives a first reference voltage controlling the first transistor to conduct a first selected current, and a control terminal of the second transistor receives a second reference voltage controlling the second transistor to conduct a second selected current;
wherein a selected tap point in the first conducting leg and a selected tap point in the second conducting leg are connected in common to receive a common mode voltage;
wherein the first differential gain signal corresponds to a differential voltage across a selected tap point in the first conducting leg and a selected tap point in the second conducting leg of a first digital-to-analog converter;
and wherein the second differential gain signal corresponds to a differential voltage across a selected tap point in the first conducting leg and a selected tap point in the second conducting leg of a second digital-to-analog converter.

8. The circuit of claim 7 , wherein the first and second reference voltages are DC voltages;
and wherein the first and second differential gain signals are DC differential voltages.

9. The circuit of claim 7 , wherein the first and second reference voltages applied to the first digital-to-analog converter are periodic signals at a second frequency and at a phase angle of 180° from one another;
wherein the first and second reference voltages applied to the second digital-to-analog converter are periodic signals at a second frequency and at a phase angle of 180° from one another, and at a phase angle of 90° from the reference voltages applied to the first digital-to-analog converter;
wherein the first and second differential gain signals are periodic signals at the second frequency and at a phase angle of 90° from one another;
and wherein the combined periodic signal has a component at the first frequency and a component at the second frequency.

10. The circuit of claim 9 , wherein the phase angle of the combined periodic signal corresponds to the inverse tangent of a ratio of the second differential gain signal to the first differential gain signal.

11. The circuit of claim 1 , wherein the load has a first end coupled to the second end of the conduction path of a first transistor in each of the first and third transistor pairs, and a second end coupled to the second end of the conduction path of a first transistor in each of the second and fourth transistor pairs.

12. The circuit of claim 11 , wherein the load comprises an inductor.

13. The circuit of claim 1 , wherein the load comprises a transformer, the transformer comprising:
a first primary inductor coupled between the second end of the conduction path of the first transistor in the first transistor pair and the second end of the conduction path of the first transistor in the second transistor pair;
a second primary inductor coupled between the second end of the conduction path of the first transistor in the third transistor pair and the second end of the conduction path of the first transistor in the fourth transistor pair; and
a secondary inductor connected between an output node and a reference voltage, the secondary inductor coupled to the first primary inductor according to a first coupling factor, and coupled to the second primary inductor according to a second coupling factor;
and wherein the phase angle of the combined periodic signal also corresponds to a relationship of the first and second coupling factor.

14. The circuit of claim 13 , wherein the circuit is realized in an integrated circuit;
wherein the first primary conductor comprise

Assignees

• Texas Instruments Inc

Inventors

• Chakraborty Sudipto

Classifications

• H03K2005/00286

  Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency · CPC title

• H03K5/01

  Shaping pulses (discrimination against noise or interference H03K5/125) · CPC title

• H03D7/1441 Primary

  using field-effect transistors (H03D7/145 takes precedence) · CPC title

• H03H11/20

  Two-port phase shifters providing an adjustable phase shift · CPC title

• H03D7/1458

  Double balanced arrangements, i.e. where both input signals are differential · CPC title