Composite semiconductor device with different channel widths

Patent metadata

Field	Value
Publication number	US-9601614-B2
Application number	US-201514669415-A
Country	US
Kind code	B2
Filing date	Mar 26, 2015
Priority date	Mar 26, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures.

First claim

The invention claimed is:

1. A device comprising:
a semiconductor substrate;
a first constituent transistor comprising a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another; and
a second constituent transistor comprising a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another;
wherein the first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another;
wherein each transistor structure of the first and second pluralities of transistor structures comprises a plurality of source regions and a plurality of body contact regions disposed in an alternating arrangement with the plurality of source regions along a lateral dimension of the device; and
wherein each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures due to a layout difference in the alternating arrangement between the first and second pluralities of transistor structures.

2. The device of claim 1 , wherein the second plurality of transistor structures are laterally surrounded by the first plurality of transistor structures.

3. The device of claim 1 , wherein the second plurality of transistor structures are centered within the first plurality of transistor structures.

4. The device of claim 1 , wherein the first and second pluralities of transistor structures are not electrically isolated from one another.

5. The device of claim 1 , wherein the first and second constituent transistors are laterally diffused metal-oxide-semiconductor (LDMOS) transistors.

6. The device of claim 1 , wherein:
each transistor structure of the first and second pluralities of transistor structures comprises a body region in which a channel is formed during operation;
the channel of each transistor structure of the first and second pluralities of transistor structures is oriented in a first lateral direction; and
the first and second constituent transistors are laterally contiguous with one another in a second lateral direction orthogonal to the first lateral direction.

7. The device of claim 1 , wherein a respective transistor structure of the first plurality of transistor structures is aligned with a respective transistor structure of the second plurality of transistor structures such that the respective transistor structures share a common gate supported by the semiconductor substrate.

8. The device of claim 1 , wherein the second constituent transistor is disposed in an inner area and the first constituent transistor is disposed outwardly from the inner area.

9. The device of claim 1 , wherein the layout difference incorporates a plurality of shallow trench isolation regions into the alternating arrangement for the second plurality of transistor structures to establish the lower resistance of each transistor structure of the first plurality of transistor structures.

10. A device comprising:
a semiconductor substrate;
a first constituent transistor comprising a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another; and
a second constituent transistor comprising a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another;
wherein the first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another;
wherein each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region of operation than each transistor structure of the second plurality of transistor structures; and
wherein an effective channel width of each transistor structure of the first plurality of transistor structures is larger than an effective channel width of each transistor structure of the second plurality of transistor structures.

11. The device of claim 10 , wherein each transistor structure of the first and second pluralities of transistor structures comprises a plurality of source regions and a plurality of body contact regions disposed in an alternating arrangement with the plurality of source regions along a lateral dimension of the device.

12. The device of claim 11 , wherein the alternating arrangement establishes the effective channel width of each transistor structure.

13. The device of claim 11 , wherein, in the second plurality of transistor structures, each source region of the plurality of source regions has a smaller size in a channel-establishing dimension than each body contact region of the plurality of body contact regions.

14. A device comprising:
a semiconductor substrate;
a first constituent transistor comprising a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another; and
a second constituent transistor comprising a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another;
wherein the first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another; and
wherein an effective channel width of each transistor structure of the first plurality of transistor structures is larger than an effective channel width of each transistor structure of the second plurality of transistor structures.

15. The device of claim 14 , wherein each transistor structure of the first and second pluralities of transistor structures comprises a plurality of source regions and a plurality of body contact regions disposed in an alternating arrangement with the plurality of source regions along a lateral dimension of the device.

16. The device of claim 15 , wherein the alternating arrangement establishes the effective channel width of each transistor structure.

17. The device of claim 15 , wherein:
the alternating arrangement establishes, for each transistor structure of the first and second plurality of transistor structures, a collective size of the plurality of body contact regions in a channel-establishing dimension and a collective size of the plurality of source regions in the channel-establishing dimension; and
for each transistor structure of the second plurality of transistor structures, the collective size of the plurality of body contact regions is greater than the collective size of the plurality of source regions.

18. The device of claim 14 , wherein the second plurality of transistor structures are laterally surrounded by the first plurality of transistor structures.

19. The device of claim 14 , wherein the second constituent transistor is disposed in an inner area and the first constituent transistor is disposed outwardly from the inner area.

20. A device comprising:
a semiconductor substrate;
a first constituent transistor comprising a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another; and
a second constituent transistor comprising a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another;
wherein the first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another;
wherein each transistor structure of the first plurality of transistor structures has a lower resistance in

Assignees

• Min Won Gi
• Rodriquez Pete
• Yang Hongning
• Zuo Jiang-Kai
• Nxp Usa Inc

Inventors

• Min Won Gi
• Rodriquez Pete
• Yang Hongning
• Zuo Jiang-Kai

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H01L29/0696

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/7816 Primary

  Electricity · mapped topic

• H01L29/7835

  Electricity · mapped topic