Semiconductor device with enhanced strain

Patent metadata

Field	Value
Publication number	US-9601594-B2
Application number	US-201113295178-A
Country	US
Kind code	B2
Filing date	Nov 14, 2011
Priority date	Nov 14, 2011
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate that is disposed over the substrate. The substrate has a recess. The semiconductor device includes a trench liner that is coated along the recess. The trench liner contains a semiconductor crystal material. The trench liner directly abuts the source/drain stressor device. The semiconductor device also includes a dielectric trench component that is disposed on the trench liner and filling the recess. The semiconductor device includes a source/drain stressor device that is disposed in the substrate. The source/drain stressor device is disposed between the gate and the trench liner.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming a first recess in a semiconductor substrate;
forming a liner layer along the first recess, the liner layer containing a semiconductor crystal material that is different from a material of the substrate, wherein the semiconductor crystal material is a III-V group compound or a II-VI group compound;
thereafter filling the first recess with a dielectric material, the dielectric material being formed on the liner layer so as to be at least partially surrounded by the liner layer; and
forming a source/drain component in the substrate, the source/drain component being in physical contact with the liner layer, wherein the forming of the source/drain component includes:
etching a second recess in the substrate, wherein the etching is performed using a high etching selectivity between the substrate and the III-V group compound of the liner layer or between the substrate and the II-VI group compound of the liner layer, so that the substrate is etched without substantially removing the liner layer; and
growing the source/drain component in the second recess, wherein the etching the second recess and the growing are performed such that at a first segment of a side surface of the source/drain component is in direct contact with the liner layer, and a second segment of the side surface is separated from the liner layer by a portion of the semiconductor substrate.

2. The method of claim 1 , wherein the physical contact between the liner layer and the source/drain component causes stress to the source/drain component.

3. The method of claim 1 , wherein the forming the source/drain component includes:
epi-growing one of: a silicon germanium material and a silicon carbide material in the second recess.

4. The method of claim 1 , further including: before the forming the source/drain component, forming a gate structure over the substrate.

5. The method of claim 3 , wherein the epi-growing is performed such that the silicon germanium material or the silicon carbide material is grown to protrude out of the substrate.

6. A method of fabricating a semiconductor device, comprising:
forming a first opening in a semiconductor substrate;
forming a liner layer over the semiconductor substrate, the liner layer containing a III-V group compound material or a II-VI group compound material, the liner layer partially filling the first opening;
filling the first opening with a dielectric material, the dielectric material being formed over the liner layer;
forming, after the filling the first opening, a second opening in the semiconductor substrate, the second opening being formed without substantially removing the liner layer;
performing a polishing process until the dielectric material, the liner layer, and the semiconductor substrate have co-planar upper surfaces; and
forming a source/drain in the second opening;
wherein the forming the second opening and the forming the source/drain are performed such that at a first segment of a side surface of the source/drain is in direct contact with the liner layer, and a second segment of the side surface is separated from the liner layer by a portion of the semiconductor substrate.

7. The method of claim 6 , wherein the forming the source/drain comprises forming the source/drain to be in physical contact with the liner layer such that stress is delivered to the source/drain due to the physical contact.

8. The method of claim 6 , wherein the forming the source/drain includes epi-growing one of: a silicon germanium material and a silicon carbide material in the second opening.

9. The method of claim 8 , wherein the epi-growing is performed such that the silicon germanium material or the silicon carbide material is grown to protrude out of the semiconductor substrate.

10. The method of claim 6 , further comprising: before the forming the source/drain, forming a gate structure over the semiconductor substrate.

11. The method of claim 6 , wherein the forming the gate structure comprises forming a high-k metal gate (HKMG) structure.

12. The method of claim 6 , wherein the filling the first opening comprises completely filling the first opening with the dielectric material, and further comprising polishing the dielectric material to form a shallow trench isolation (STI) in the first opening.

13. The method of claim 6 , wherein the forming the source/drain comprises forming a source/drain having a different material composition than the semiconductor substrate.

14. The method of claim 6 , wherein the source/drain is formed to be completely isolated from the dielectric material filling the first opening in a cross-sectional side view.

15. The method of claim 6 , wherein the source/drain is formed to directly abut a portion of the liner layer that is formed on a sidewall of the first opening.

16. A method of fabricating a semiconductor device, comprising:
forming a trench in a semiconductor substrate;
forming a liner layer containing a III-V group compound material or a II-VI group compound material over the substrate, the liner layer partially filling the trench;
forming a shallow trench isolation (STI) by filling the first opening with a dielectric material and polishing the dielectric material, the STI being partially surrounded by the liner layer;
thereafter etching a recess in the semiconductor substrate using a high etching selectivity between the semiconductor substrate and the III-V group compound material of the liner layer or between the semiconductor substrate and the II-VI group compound material of the liner layer, so that the semiconductor substrate is etched without substantially etching the liner layer; and
growing a source/drain in the recess such that the source/drain is in direct physical contact with the liner layer and separated from the STI, the source/drain and the semiconductor substrate having different material compositions;
wherein the etching the recess and the growing are performed such that at a first segment of a side surface of the source/drain is in direct contact with the liner layer, and a second segment of the side surface is separated from the liner layer by a portion of the semiconductor substrate.

17. The method of claim 16 , wherein the growing of the source/drain comprises growing silicon germanium or silicon carbide in the recess via an epitaxial growth process.

18. The method of claim 16 , wherein the growing of the source/drain is performed such that the source/drain is grown to protrude out of the semiconductor substrate.

19. The method of claim 16 , further comprising: before the growing of the source/drain, forming a gate structure over the semiconductor substrate.

20. The method of claim 19 , wherein the forming the gate structure comprises forming a high-k metal gate (HKMG) structure.

Assignees

• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Cheng-Hsien
• Ko Chih-Hsin
• Wann Clement Hsingjen

Classifications

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D62/021

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title