Semiconductor device for reducing propagation time of gate input signals

Patent metadata

Field	Value
Publication number	US-9601573-B2
Application number	US-201514681779-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Apr 14, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A gate pad is disposed on a semiconductor layer composed of an n + type substrate, an n − type epitaxial layer, and a p − type body layer. The gate pad is disposed at the center portion of the semiconductor layer as viewed in plan. A plurality of unit cells that compose a trench type MOSFET element are provided in the semiconductor layer. The plurality of unit cells are arranged in the radial direction about the gate pad as viewed in plan. A gate electrode of a unit cell (center-side unit cell) that is proximate to the gate pad is electrically connected to the gate pad. Gate electrodes of unit cells that are adjacent to each other in the radial direction are connected to each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor layer;
a gate pad disposed on the semiconductor layer and formed at a center portion of the semiconductor layer as viewed in plan from a thickness direction of the semiconductor layer; and
a plurality of unit cells formed in the semiconductor layer to each compose a transistor element that is either a metal oxide semiconductor (MOS) field effect transistor element or an insulated gate bipolar transistor element, and arranged in a radial direction about the gate pad as viewed in plan, wherein
a gate electrode of a unit cell that is proximate to the gate pad, among the plurality of unit cells arranged in the radial direction, is electrically connected to the gate pad, and gate electrodes of unit cells that are adjacent to each other in the radial direction are connected to each other,
the unit cells each have a regular hexagonal shape as viewed in plan,
a source region of the unit cells other than the unit cells proximate to the gate pad is formed in a regular hexagonal ring shape as viewed in plan, and a source region of the unit cells proximate to the gate pad is formed in a partially missing regular hexagonal ring shape as viewed in plan.

Assignees

• Jtekt Corp

Inventors

• Takeda Yasuhide
• Wakita Yasuyuki

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title