Deep trench isolation

Patent metadata

Field	Value
Publication number	US-9601564-B2
Application number	US-201615132329-A
Country	US
Kind code	B2
Filing date	Apr 19, 2016
Priority date	Mar 13, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.

First claim

What is claimed is:

1. An integrated semiconductor device, comprising:
a substrate of a first conductivity type;
a buried layer located over the substrate;
an isolated region located over a first portion of the buried layer;
an isolation trench located around the isolated region; and
a punch-through structure located around at least a portion of the isolation trench, the punch-through structure including:
a second portion of the buried layer,
a first region located over the second portion of the buried layer, the first region having the first conductivity type, and
a second region located over the first region, the second region having a second conductivity type.

2. The device of claim 1 , wherein, when the isolated region is set to a greater than zero potential with respect to the substrate, a voltage across the second portion of the buried layer to the substrate is less than a voltage across the first portion of the buried layer to the substrate.

3. The device of claim 1 , including a second isolation trench located around the punch-through structure.

4. The device of claim 3 , including a second punch-through structure located around at least a portion of the second isolation trench, the second punch-through structure including a third portion of the buried layer.

5. The device of claim 4 , wherein, when the isolated region is set to the greater than zero potential with respect to the substrate, a voltage across the third portion of the buried layer to the substrate is less than a voltage across the first portion of the buried layer to the substrate.

6. The device of claim 4 , wherein the second punch-through structure includes:
a third region located over the third portion of the buried layer, the third region having the first conductivity type, and
a fourth region located over the third region, the fourth region having the second conductivity type.

7. The device of claim 6 , wherein a depth of the first region of the first punch-through structure is greater than a depth of the third region of the second punch-through structure.

8. The device of claim 4 , including a third isolation trench located around the second punch-through structure.

9. The device of claim 1 , including a polysilicon material disposed within the isolation trench.

10. The device of claim 9 , including an oxide located around the polysilicon material.

11. The device of claim 10 , wherein the punch-through structure is configured to pull-up a potential of the polysilicon material disposed within the isolation trench when the isolated region is set to the greater than zero potential with respect to the substrate.

12. The device of claim 1 , including a transistor, a resistor, a diode, or a capacitor located at least partially within the isolated region.

13. The device of claim 1 , including an insulation region located within the isolated region, the insulation region having a conductivity type being the same as a conductivity type of the buried layer.

14. An integrated semiconductor device, comprising:
a substrate of a first conductivity type;
a buried layer located over the substrate;
an isolated region located over a first portion of the buried layer, the isolated region having a conductivity type opposite of the first conductivity type;
an isolation trench located around the isolated region; and
a punch-through structure located around at least a portion of the isolation trench, the punch-through structure including:
a second portion of the buried layer,
a first region located over the second portion of the buried layer, the first region having the first conductivity type, and
a second region located over the first region, the second region having a second conductivity type.

15. The device of claim 14 , including a second isolation trench located around the punch-through structure.

16. The device of claim 15 , including a second punch-through structure located around at least a portion of the second isolation trench, the second punch-through structure including a third portion of the buried layer.

17. The device of claim 16 , wherein the second punch-through structure includes:
a third region located over the third portion of the buried layer, the third region having the first conductivity type, and
a fourth region located over the third region, the fourth region having the second conductivity type.

18. The device of claim 17 , wherein a depth of the first region of the first punch-through structure is greater than a depth of the third region of the second punch-through structure.

19. The device of claim 14 , including an insulation region located within the isolated region, the insulation region having a conductivity type being the same as a conductivity type of the buried layer.

20. An integrated semiconductor device, comprising:
a substrate of a first conductivity type;
a buried layer located over the substrate;
an isolated region located over a first portion of the buried layer;
a first isolation trench located around the isolated region;
a second isolation trench located around the first isolation trench; and
a punch-through structure located between at least a portion of the first isolation trench and a portion of the second isolation trench, the punch-through structure including:
a second portion of the buried layer,
a first region located over the second portion of the buried layer, the first region having the first conductivity type, and
a second region located over the first region, the second region having a second conductivity type.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Cheng Xu
• Blomberg Daniel J
• Zhang Zhihong
• Zuo Jiang-Kai

Classifications

• H10W10/0148

  comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers · CPC title

• H10W10/041

  of isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/40

  Isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title