Semiconductor device having sacrificial layer pattern with concave sidewalls and method fabricating the same

Patent metadata

Field	Value
Publication number	US-9601496-B2
Application number	US-201314109159-A
Country	US
Kind code	B2
Filing date	Dec 17, 2013
Priority date	Jan 2, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first conductive line;
a second conductive line formed at substantially the same height from a substrate as the first conductive line, wherein the first and second conductive lines are spaced apart from each other; and
a first sacrificial layer pattern disposed between the first and second conductive lines and formed at substantially the same height from the substrate as the first and second conductive lines,
wherein the first sacrificial layer pattern has at least one concave sidewall.

2. The semiconductor device of claim 1 , wherein the first and second conductive lines each have at least one sidewall which is curved toward the first sacrificial layer pattern.

3. The semiconductor device of claim 1 , further comprising:
a third conductive line disposed between the first conductive line and the substrate;
a fourth conductive line disposed between the second conductive line and the substrate; and
gate interlayer dielectric layers disposed between the first conductive line and the third conductive line and between the second conductive line and the fourth conductive line,
wherein an etch rate of the first sacrificial layer pattern is different from an etch rate of the gate interlayer dielectric layers.

4. A semiconductor device, comprising:
a first conductive line;
a second conductive line formed at substantially the same height from a substrate as the first conductive line, wherein the first and second conductive lines are spaced apart from each other; and
a first sacrificial layer pattern disposed between the first and second conductive lines,
a third conductive line disposed between the first conductive line and the substrate;
a fourth conductive line disposed between the second conductive line and the substrate; and
gate interlayer dielectric layers disposed between the first conductive line and the third conductive line and between the second conductive line and the fourth conductive line,
a second sacrificial layer pattern disposed between the third conductive line and the fourth conductive line,
wherein the first sacrificial layer pattern has at least one concave sidewall,
wherein an etch rate of the first sacrificial layer pattern is different from an etch rate of the gate interlayer dielectric layers, and
wherein the second sacrificial layer pattern has at least one concave sidewall.

5. The semiconductor device of claim 3 , wherein the third conductive line and the fourth conductive line contact each other.

6. The semiconductor device of claim 1 ,
further comprising a dummy active pattern disposed between the first conductive line and the second conductive line,
wherein the dummy active pattern contacts the first sacrificial layer pattern.

7. The semiconductor device of claim 1 ,
further comprising a plurality of gate interlayer dielectric layers,
wherein the first and second conductive lines and the first sacrificial layer pattern is interposed between an adjacent pair of the gate interlayer dielectric layers.

8. A semiconductor device comprising:
a plurality of lower selection lines that are parallel to each other on a substrate;
a plurality of word lines disposed above the lower selection lines, the word lines spaced apart from the lower selection lines, wherein the word lines are parallel to each other;
a plurality of upper selection lines disposed above the word lines, the upper selection lines spaced apart from the word lines, wherein the upper selection lines are parallel to each other; and
a sacrificial layer pattern disposed between the upper selection lines and formed at substantially the same height from the substrate as the upper selection lines,
wherein the sacrificial layer pattern has at least one concave sidewall.

9. The semiconductor device of claim 8 ,
further comprising a buried insulation pattern spaced apart from the sacrificial layer pattern, the buried insulation pattern disposed between the upper selection lines,
wherein the buried insulation pattern has flat side walls.

10. The semiconductor device of claim 9 , wherein the buried insulation pattern is disposed between the word lines and between the lower selection lines.

11. The semiconductor device of claim 9 , wherein the buried insulation pattern is formed of a material different from the sacrificial layer pattern.

12. The semiconductor device of claim 8 ,
further comprising a plurality of gate interlayer dielectric layers disposed on a top surface of the plurality of upper selection lines, between the upper selection line and the word line,
wherein the first sacrificial layer pattern is interposed between an adjacent pair of the gate interlayer dielectric layers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sanghoon
• Go Hyunyong
• Kim Sunggil
• An Kyong-Won
• Lee Woosung
• Cho Yongseok

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H01L2924/0002

  Electricity · mapped topic

• H01L27/10855 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic