Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
US9601473B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9601473-B2 |
| Application number | US-201514928874-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 30, 2015 |
| Priority date | Oct 15, 2013 |
| Publication date | Mar 21, 2017 |
| Grant date | Mar 21, 2017 |
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A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT cassette within the module includes a set of shims, two contact pins, and an IGBT die. The first contact pin provides part of a first electrical connection between the gate module terminal and the IGBT gate pad. The second contact pin provides part of a second electrical connection between the auxiliary module terminal and a shim that in turn contacts the IGBT emitter pad. The electrical connection between the auxiliary emitter terminal and each emitter pad of the many IGBTs is a balanced impedance network. The balanced network is not part of the high current path through the module. By supplying a gate drive signal between the gate and auxiliary emitter terminals, simultaneous IGBT turn off in high speed and high current switching conditions is facilitated.
Opening claim text (preview).
What is claimed is: 1. A power semiconductor device module comprising: a top plate member; a bottom plate member having a plurality of pedestals; a plurality of semiconductor device dice, wherein each of the semiconductor device dice is positioned above a corresponding one of the plurality of pedestals between the bottom plate member and the top plate member, and wherein each of the semiconductor device dice has an emitter pad and a gate pad; an auxiliary emitter terminal, wherein the auxiliary emitter terminal is coupled via a branched network to the emitter pads of the semiconductor device dice; and a main emitter terminal, wherein the main emitter terminal is coupled through the pedestals to the emitter pads of the semiconductor device dice, and wherein the branched network does not extend through any of the pedestals. 2. The power semiconductor device module of claim 1 , wherein the branched network extends through a first plurality of spring loaded contact pins, and wherein the main emitter terminal is coupled through no spring loaded contact pin to the emitter pad of any of the semiconductor device dice. 3. The power semiconductor device module of claim 2 , further comprising: a gate terminal, wherein the gate terminal is coupled through a second plurality of spring loaded contact pins to the gate pads of the semiconductor device dice. 4. The power semiconductor device module of claim 1 , wherein the main emitter terminal is a surface of the bottom plate member. 5. The power semiconductor device module of claim 1 , wherein the main emitter terminal is a surface of a circular bottom lid, and wherein the bottom lid is attached to the bottom plate member. 6. The power semiconductor device module of claim 1 , wherein the semiconductor device dice are Insulated Gate Bipolar Transistor (IBGT) device dice. 7. The power semiconductor device module of claim 1 , wherein the power semiconductor device module comprises a Printed Circuit Board (PCB), and wherein the branched network extends through the PCB. 8. The power semiconductor device module of claim 1 , further comprising: a plurality of insulative four-sided frames, wherein each of the four-sided frames is disposed around a corresponding one of the plurality of pedestals. 9. The power semiconductor device module of claim 1 , wherein the power semiconductor device module is a disc-shaped press pack module. 10. A power semiconductor device module comprising: a top plate member; a plurality of pedestals; a plurality of semiconductor device dice, wherein each of the semiconductor device dice is positioned above a corresponding one of the plurality of pedestals between the pedestal and the top plate member, and wherein each of the semiconductor device dice has an emitter pad and a gate pad; a main emitter module terminal; an auxiliary emitter module terminal; first means for coupling the main emitter module terminal through the pedestals to the emitter pads of the semiconductor device dice; and second means for coupling the auxiliary emitter module terminal through a conductive path to the emitter pads of the semiconductor device dice, wherein the conductive path includes a plurality of contact pins, and wherein the conductive path does not extend through any of the pedestals. 11. The power semiconductor device module of claim 10 , wherein the first means comprises no contact pins, and wherein the second means comprises a printed circuit board, a plurality of resistors, and a plurality of shims in addition to the plurality of contact pins. 12. The power semiconductor device module of claim 10 , wherein the semiconductor device dice are Insulated Gate Bipolar Transistor (IBGT) device dice. 13. The power semiconductor device module of claim 10 , further comprising: a plurality of insulative four-sided frames, wherein each of the four-sided frames is disposed around a corresponding one of the plurality of pedestals. 14. The power semiconductor device module of claim 10 , wherein the power semiconductor device module is a disc-shaped press pack module. 15. A power semiconductor device module comprising: a top plate member; a bottom plate member having a plurality of pedestals; a plurality of semiconductor device dice, wherein each of the semiconductor device dice is positioned above a corresponding one of the plurality of pedestals between the bottom plate member and the top plate member, and wherein each of the semiconductor device dice has an emitter pad and a gate pad; an auxiliary emitter terminal, wherein the auxiliary emitter terminal is coupled via a branched network to the emitter pads of the semiconductor device dice; a main emitter terminal, wherein the main emitter terminal is coupled through the pedestals to the emitter pads of the semiconductor device dice, and wherein the branched network does not extend through any of the pedestals; and a plurality of insulative four-sided frames, wherein each of the four-sided frames is disposed around a corresponding one of the plurality of pedestals, wherein each of the four-sided frames has a first channel and a second channel, wherein a first spring-loaded contact pin is disposed in the first channel, and wherein a second spring-loaded contact pin is disposed in the second channel. 16. The power semiconductor device module of claim 15 , wherein the first spring-loaded contact pin contacts the gate pad of one of the semiconductor device dice disposed in the frame, wherein the second spring-loaded contact pin contacts a shim disposed in the frame, and wherein the shim is in physical contact with the emitter pad of the one of the semiconductor device dice. 17. A power semiconductor device module comprising: a top plate member; a bottom plate member having a plurality of pedestals; a plurality of semiconductor device dice, wherein each of the semiconductor device dice is positioned above a corresponding one of the plurality of pedestals between the bottom plate member and the top plate member, and wherein each of the semiconductor device dice has an emitter pad and a gate pad; an auxiliary emitter terminal, wherein the auxiliary emitter terminal is coupled via a branched network to the emitter pads of the semiconductor device dice; and a main emitter terminal, wherein the main emitter terminal is coupled through the pedestals to the emitter pads of the semiconductor device dice, wherein the branched network does not extend through any of the pedestals, wherein a first conductive path extends from a gate terminal of the power semiconductor device module, and through a first spring-loaded contact pin, and to the gate pad of one of the semiconductor device dice, and wherein a second conductive path extends from the auxiliary emitter terminal, and through a second spring-loaded contact pin, through a shim, and to the emitter pad of one of the semiconductor device dice.
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