Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9601433-B2
Application number	US-201514876284-A
Country	US
Kind code	B2
Filing date	Oct 6, 2015
Priority date	Jun 11, 2007
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

First claim

What is claimed is:

1. A manufacturing method of semiconductor device comprising the steps of:
(a) forming a first field effect transistor having a first gate insulation film, a first gate electrode, a first impurity region and a second impurity region on a semiconductor substrate;
(b) forming a first insulation film covering the first field effect transistor over the semiconductor substrate;
(c) planarizing a surface of the first insulation film;
(d) after the step (c), forming a second insulation film over the first insulation film;
(e) forming a first contact hole which penetrates the first insulation film and the second insulation film and reaches the first impurity region, and forming a second contact hole which penetrates the first insulation film and the second insulation film and reaches the second impurity region;
(f) embedding a conductive film into the first contact hole to form a first plug, and embedding a conductive film into the second contact hole to form a second plug; and
(g) forming a first wire connected to the first plug and a second wire connected to the second plug,
wherein the first insulation film includes a third insulation film and a fourth insulation film,
the step (b) includes the steps of:
(b1) forming the third insulation film covering the first field effect transistor by use of first plasma; and
(b2) forming the fourth insulation film over the third insulation film by use of second plasma, and
a density of the first plasma is higher than a density of the second plasma.

2. The manufacturing method of a semiconductor device according to claim 1 ,
wherein in the step (d), the second insulation film is formed by use of third plasma, and
the density of the first plasma is higher than a density of the third plasma.

3. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the first gate electrode and the first wire are not overlapped planarly with each other, and
the first gate electrode and the second wire are not overlapped planarly with each other.

4. The manufacturing method of a semiconductor device according to claim 1 ,
wherein a drive voltage of the first field effect transistor is 20 V or more.

5. The manufacturing method of a semiconductor device according to claim 1 ,
wherein the first field effect transistor has a field relaxing layer formed in the semiconductor substrate, and
a part of the first gate electrode runs onto the field relaxing layer.

6. The manufacturing method of a semiconductor device according to claim 5 ,
wherein a part of the field relaxing layer protrudes from the semiconductor substrate.

7. The manufacturing method of a semiconductor device according to claim 1 ,
wherein when a distance from an interface between the semiconductor substrate and the first gate insulation film to an upper surface of the first gate electrode is defined as “a” and a distance from the upper surface of the first gate electrode to an upper surface of the second insulation film is defined as “b”, a relation of a>b is established.

8. The manufacturing method of a semiconductor device according to claim 1 ,
wherein a second field effect transistor having a second gate insulation film, a second gate electrode, a third impurity region and a fourth impurity region is formed on the semiconductor substrate,
in the step (e), a third contact hole which penetrates the first insulation film and the second insulation film and reaches the third impurity region, and a fourth contact hole which penetrates the first insulation film and the second insulation film and reaches the fourth impurity region are further formed,
in the step (f), a third plug is further formed by embedding a conductive film into the third contact hole and a fourth plug is further formed by embedding a conductive film into the fourth contact hole,
in the step (g), a third wire connected to the third plug and a fourth wire connected to the fourth plug are further formed, and
a film thickness of the first gate insulation film is larger than a film thickness of the second gate insulation film.

9. A manufacturing method of a semiconductor device comprising the steps of:
(a) forming a first field effect transistor having a first gate insulation film, a first gate electrode, a first impurity region and a second impurity region on a semiconductor substrate;
(b) forming a first insulation film covering the first field effect transistor over the semiconductor substrate;
(c) planarizing a surface of the first insulation film;
(d) after the step (c), forming a second insulation film over the first insulation film;
(e) forming a first contact hole which penetrates the first insulation film and the second insulation film and reaches the first impurity region, and forming a second contact hole which penetrates the first insulation film and the second insulation film and reaches the second impurity region;
(f) embedding a conductive film into the first contact hole to form a first plug, and embedding a conductive film into the second contact hole to form a second plug; and
(g) forming a first wire connected to the first plug and a second wire connected to the second plug,
wherein a drive voltage of the first field effect transistor is 20 V or more.

10. The manufacturing method of a semiconductor device according to claim 9 ,
wherein the first gate electrode and the first wire are not overlapped planarly with each other, and
the first gate electrode and the second wire are not overlapped planarly with each other.

11. The manufacturing method of a semiconductor device according to claim 9 ,
wherein the first field effect transistor has a field relaxing layer formed in the semiconductor substrate, and
a part of the first gate electrode runs onto the field relaxing layer.

12. The manufacturing method of a semiconductor device according to claim 11 ,
wherein a part of the field relaxing layer protrudes from the semiconductor substrate.

13. The manufacturing method of a semiconductor device according to claim 9 ,
wherein when a distance from an interface between the semiconductor substrate and the first gate insulation film to an upper surface of the first gate electrode is defined as “a” and a distance from the upper surface of the first gate electrode to an upper surface of the second insulation film is defined as “b”, a relation of a>b is established.

14. The manufacturing method of a semiconductor device according to claim 9 ,
wherein a second field effect transistor having a second gate insulation film, a second gate electrode, a third impurity region and a fourth impurity region is formed on the semiconductor substrate,
in the step (e), a third contact hole which penetrates the first insulation film and the second insulation film and reaches the third impurity region, and a fourth contact hole which penetrates the first insulation film and the second insulation film and reaches the fourth impurity region are further formed,
in the step (f), a third plug is further formed by embedding a conductive film into the third contact hole and a fourth plug is further formed by embedding a conductive film into the fourth contact hole,
in the step (g), a third wire connected to the third plug and a fourth wire connected to the fourth plug are further formed, and
a film thickness of the first gate insulation film is larger than a film thickness of the second gate insulation film.

15. A manufacturing method of a semiconductor device comprising the steps of:
(a) forming a first field effect transistor having a first gate insulation film, a first gate electrode

Assignees

• Renesas Electronics Corp

Inventors

• Terada Yusuke
• Toyokawa Shigeya
• Maeda Atsushi

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W10/0143

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title