BBUL material integration in-plane with embedded die for warpage control

Patent metadata

Field	Value
Publication number	US-9601421-B2
Application number	US-201113976356-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die. A method of forming a package and an apparatus including a computing device including a package are also disclosed.

First claim

The invention claimed is:

1. An apparatus comprising:
a die comprising a first side and an opposite second side comprising a device side with contact points and lateral sidewalls defining a thickness of the die;
a primary core having a cavity therein, wherein the die is positioned in the cavity such that the primary core is adjacent at least a pair of the lateral sidewalls of the die, the primary core comprising a material having a coefficient of thermal expansion similar to a coefficient of thermal expansion of the die;
a build-up carrier coupled to the second side of the die, the build-up carrier comprising a plurality of alternating layers of conductive material and insulating material wherein at least one of the layers of conductive material is coupled to one of the contact points of the die at a point outside the cavity of the primary core and a first plurality of contacts on a surface of the build-up carrier and coupled to at least one of the plurality of alternating layers of conductive material; and
a second plurality of contacts comprising multilayer contacts disposed within and on a surface of the primary core and coupled to at least one of the plurality of alternating layers of a conductive material.

2. The apparatus of claim 1 , wherein the material of the primary core achieves a predetermined warpage target for at least one of a given temperature, package architecture, number of package layers, body size and a die to package area ratio.

3. The apparatus of claim 1 , wherein the material of the primary core is different than the insulating material of the build-up carrier.

4. The apparatus of claim 1 , wherein a thickness of the primary core is similar to a thickness of the die.

5. The apparatus of claim 1 , wherein the die comprises four lateral side walls and the primary core is adjacent each of the four lateral side walls.

6. The apparatus of claim 1 , wherein the first side of the die defines a plane and a thickness of the primary core defines a surface that is no greater than the plane of the first surface of the die.

7. The apparatus of claim 1 , wherein the primary core is disposed on the first surface of the die.

8. An apparatus comprising:
a computing device comprising a package comprising:
a microprocessor comprising a first side and an opposite second side comprising a device side with contact points and lateral sidewalls defining a thickness of the microprocessor;
a primary core having a cavity therein, wherein the microprocessor is positioned in the cavity such that the primary core is adjacent at least a pair of the lateral sidewalls of the microprocessor, the primary core comprising a material having a coefficient of thermal expansion similar to a coefficient of thermal expansion of the die; and
a build-up carrier coupled to the second side of the microprocessor, the build-up carrier comprising:
a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the microprocessor at a point outside the cavity of the primary core; and
a first plurality of accessible contacts opposite a microprocessor side of the build-up carrier and a second plurality of contacts on the microprocessor side of the build-up carrier, wherein the second plurality of contacts comprise multilayer contacts disposed within and on a surface of the primary core; and

a printed circuit board coupled to at least a portion of the first plurality of accessible contacts of the package.

9. The apparatus of claim 8 , further comprising:
a secondary device coupled to the second plurality of contacts.

10. The apparatus of claim 9 , wherein the secondary device comprises at least one memory device.

11. The apparatus of claim 8 , wherein the material of the primary core has a property and dimensions selected to target a predetermined warpage target of the combination of the microprocessor and the build-up carrier.

Assignees

• Teh Weng Hong
• Kulkarni Deepak V
• Intel Corp

Inventors

• Teh Weng Hong
• Kulkarni Deepak V

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/073

  of die-attach connectors · CPC title