Module arrangement for power semiconductor devices

Patent metadata

Field	Value
Publication number	US-9601399-B2
Application number	US-201514927006-A
Country	US
Kind code	B2
Filing date	Oct 29, 2015
Priority date	Apr 29, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A module arrangement for power semiconductor devices, including one or more power semiconductor modules, wherein the one or more power semiconductor modules include a substrate with a first surface and a second surface being arranged opposite to the first surface, wherein the substrate is at least partially electrically insulating, wherein a conductive structure is arranged at the first surface of the substrate, wherein at least one power semiconductor device is arranged on the conductive structure and electrically connected thereto, wherein the one or more modules includes an inner volume for receiving the at least one power semiconductor device which volume is hermetically sealed from its surrounding by a module enclosure, wherein the module arrangement includes an arrangement enclosure at least partly defining a volume for receiving the one or more modules, and wherein the arrangement enclosure seals covers the volume.

First claim

What is claimed:

1. A module arrangement for power semiconductor devices, comprising:
one or more power semiconductor modules, wherein the one or more power semiconductor modules each includes a substrate with a first surface and a second surface being arranged opposite to the first surface,
wherein for each of the one or more modules, the substrate is at least partially electrically insulating, a conductive structure is arranged at the first surface of the substrate, and at least one power semiconductor device is arranged on said conductive structure and electrically connected thereto,
wherein the one or more modules each comprises an inner volume for receiving the at least one power semiconductor device, the inner volume of at least one of the one or more modules being hermetically sealed from its surrounding by a module enclosure,
wherein the module arrangement comprises an arrangement enclosure at least partly defining a volume for receiving the one or more modules, wherein the arrangement enclosure covers said volume, and
wherein the arrangement enclosure hermetically seals the volume defined therefrom.

2. The module arrangement according to claim 1 , wherein each inner volume of the one or more modules is hermetically sealed from its surrounding by the respective module enclosure.

3. The module arrangement according to claim 1 , wherein the substrate of at least one module of said one or more modules comprises multiple electrical insulating layers and multiple electrical conducting layers, the electrical insulating layers and the electrical conducting layers being arranged for externally contacting said at least one power semiconductor device being comprised by said at least one module through the substrate.

4. The module arrangement according to claim 3 , wherein the electrical conducting layers connect said at least one power semiconductor device to a connection area located outside the module enclosure by a via.

5. The module arrangement according to claim 1 , wherein electrical conductors for contacting an interior of the one or more modules are guided through the module enclosure by hermetic sealings.

6. The module arrangement according to claim 1 , wherein the module enclosure and/or the arrangement enclosure comprises at least one material selected from the group consisting of AISiC and metals.

7. The module arrangement according to claim 1 , wherein the inner volume of at least one of the one or more modules is filled with a compound selected from the group consisting of silicon gel and an inert gas.

8. The module arrangement according to claim 1 , wherein the volume at least partly defined by the arrangement enclosure is filled with a compound selected from the group consisting of silicon gel and an inert gas.

9. An electrical device, comprising:
a module arrangement including one or more power semiconductor modules, wherein the one or more power semiconductor modules each includes a substrate with a first surface and a second surface being arranged opposite to the first surface,
wherein, for each of the one or more modules, the substrate is at least partially electrically insulating, a conductive structure is arranged at the first surface of the substrate, and at least one power semiconductor device is arranged on said conductive structure and electrically connected thereto,
wherein the one or more modules each comprises an inner volume for receiving the at least one power semiconductor device, the inner volume being hermetically sealed from its surrounding by a module enclosure,
wherein the module arrangement comprises an arrangement enclosure at least partly defining a volume for receiving the one or more modules, wherein the arrangement enclosure covers said volume, and
wherein the arrangement enclosure hermetically seals the volume defined therefrom.

10. The module arrangement according to claim 1 , wherein the at least one power semiconductor device comprises one of an insulated gate bipolar transistor, diode, or metal oxide semiconductor filed-effect transistor.

11. The module arrangement according to claim 1 , further comprising a base plate, wherein the arrangement enclosure and the base plate define the volume for receiving the one or more modules.

12. The module arrangement according to claim 11 , wherein the second surface of the substrate of each of the one or more modules is connected to the base plate.

13. The module arrangement according to claim 12 , wherein the second surface of the substrate of each of the one or more modules is connected to the base plate through a metallization and a solder.

14. The module arrangement according to claim 1 , wherein for each of the one or more modules, the at least one power semiconductor device is connected to the conductive structure by a solder and further bonded by wires to the conductive structure.

15. The module arrangement according to claim 1 , wherein for at least one of the one or more modules, the module enclosure is formed as one single piece.

16. The module arrangement according to claim 1 , wherein for at least one of the one or more modules, the module enclosure is formed as a frame of wall pieces and a lid connected to the wall pieces by hermetic sealings.

17. A module arrangement for power semiconductor devices, comprising:
a plurality of power semiconductor modules, each of the plurality of modules includes a substrate with a first surface and a second surface being arranged opposite to the first surface,
a base plate, the second surface of the substrate of each of the plurality of modules is connected to the base plate, and
an arrangement enclosure connected to the base plate, the arrangement enclosure and base plate define a volume for receiving the plurality of modules, the arrangement enclosure hermetically sealing the volume defined by the arrangement enclosure and the base plate,
wherein for each of the plurality of modules, the substrate is at least partially electrically insulating, a conductive structure is arranged at the first surface of the substrate, and at least one power semiconductor device is arranged on said conductive structure and electrically connected thereto,
wherein the plurality of modules each comprises an inner volume for receiving the at least one power semiconductor device, the inner volume being hermetically sealed from its surrounding by a module enclosure.

Assignees

• Abb Schweiz Ag

Inventors

• Rahimo Munaf
• Duran Hamit

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W76/17

  characterised by their materials · CPC title

• H10W74/124

  the encapsulations having cavities other than that occupied by chips · CPC title