Iterator register for structured memory

Patent metadata

Field	Value
Publication number	US-9601199-B2
Application number	US-84295810-A
Country	US
Kind code	B2
Filing date	Jul 23, 2010
Priority date	Jan 26, 2007
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain.
Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element. A local state associated with a selected iterator register is generated by performing one or more register operations relating to the selected iterator register and involving pointers in the pointer fields of the selected iterator register. A pointer-linked data structure is updated in the memory system according to the local state.

First claim

What is claimed is:

1. A memory system comprising:
a memory to store data in a pointer-linked data structure, the pointer-linked data structure including a plurality of nodes; and
a processor in communication with the memory, the processor including at least one iterator register, wherein the iterator register is to store a first pointer chain that specifies a location of a first data element within the pointer-linked data structure from a root node, of the plurality of nodes, to a leaf node, of the plurality of nodes, wherein the first pointer chain includes a first, a second, and a third pointer, wherein the first pointer points to the second pointer and the second pointer points to the third pointer; and
wherein when a subsequent access of data in the pointer-linked data structure causes a writing of a second pointer chain, associated with access of a second data element within the pointer-linked data structure, to the iterator register and the second pointer chain includes one or more same pointers as included in the first pointer chain, a first portion of the iterator register is to store only a portion of the second pointer chain not in common with the first pointer chain and a second portion of the iterator register is to retain the one or more same pointers as included in the first pointer chain.

2. The memory system of claim 1 , wherein the second pointer chain specifies a location of the second data element from the root node to a second leaf node, of the plurality of nodes.

3. A method of loading data from a computer memory system comprising:
loading into a selected iterator register, from a memory that stores one or more pointer-linked data structures, a first, a second, and a third pointer associated with a selected pointer-linked data structure, of the one or more pointer-linked data structures, wherein the first, second, and third pointers comprise a first pointer chain that specifies a location of a first data element within the selected pointer-linked data structure from a root node, of a plurality of nodes of the selected pointer-linked data structure, to a first leaf node, of the plurality of nodes, wherein the first, second, and third pointers are to be loaded into respective pointer fields included in the selected iterator register; and
loading into the selected iterator register at least a portion of a second pointer chain having two or more pointers leading to a second data element located within a second leaf node of the selected pointer-linked data structure, wherein, when the second pointer chain includes one or more same pointers as included in the first pointer chain, loading into the selected iterator register only the portion of the second pointer chain not in common with the first pointer chain and retaining the one or more same pointers as included in the first pointer chain.

4. A method of modifying data stored in a computer memory system, the method comprising:
generating a local state associated with a selected iterator register,
wherein the iterator register stores a pointer chain that specifies a location of a data element within a pointer-linked data structure from a root node, of a plurality of nodes of the pointer-linked data structure, to a leaf node, of the plurality of nodes, wherein the pointer chain includes a first, a second, and a third pointer, wherein the first pointer points to the second pointer and the second pointer points to the third pointer, wherein the first, second, and third pointers are stored in respective pointer fields of the iterator register, and wherein the iterator register subsequently stores another pointer chain that specifies a location of another data element different from the data element by storing only one or more pointers included in the another pointer chain that is different from the pointer chain when the another pointer chain and the pointer chain have one or more pointers in common and retaining the one or more pointers in common from the pointer chain;
wherein generating the local state includes performing one or more register operations relating to the selected iterator register and involving pointers in the pointer fields of the selected iterator register;
wherein the local state refers to any state in the iterator register, including a stored state within the pointer fields; and
updating the pointer-linked data structure in a memory system according to the local state.

5. The method of claim 4 , wherein the updating a pointer-linked data structure is performed atomically.

6. The method of claim 4 , further comprising translating a non-compacted pointer representation in the selected iterator register to a compacted pointer representation in the pointer-linked data structure.

7. The method of claim 4 , wherein the iterator registers each further include an element field that provides storage for the data elements.

8. The method of claim 4 , further comprising translating a compacted pointer representation in the selected iterator register to a compacted pointer representation in the pointer-linked data structure.

9. The memory system of claim 1 , wherein the iterator register comprises storage that is accessible more rapidly by the processor than the memory.

10. The memory system of claim 1 , wherein the first pointer is the same pointer included in both the first and second pointer chains.

11. The memory system of claim 1 , wherein the second pointer is the same pointer included in both the first and second pointer chains.

12. The memory system of claim 1 , wherein the first and second pointers are the same pointers included in both the first and second pointer chains.

13. The memory system of claim 1 , wherein the first pointer points to the root node.

14. The method of claim 3 , wherein the first pointer is the same pointer included in both the first and second pointer chains.

15. The method of claim 3 , wherein the second pointer is the same pointer included in both the first and second pointer chains.

16. The method of claim 3 , wherein the first and second pointers are the same pointers included in both the first and second pointer chains.

17. The method of claim 3 , wherein the first pointer points to the root node.

18. The method of claim 3 , wherein the first pointer points to the second pointer and the second pointer points to the third pointer.

19. The method of claim 4 , wherein the selected iterator register comprises storage that is accessible more rapidly by a processor than a memory.

Assignees

• Cheriton David R
• Firoozshahian Amin
• Solomatnikov Alexandre Y
• Intel Corp

Inventors

• Cheriton David R
• Firoozshahian Amin
• Solomatnikov Alexandre Y

Classifications

• G11C15/00 Primary

  Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F2212/622

  State-only directory, i.e. not recording identity of sharing or owning nodes · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title