Memory circuit provided with bistable circuit and non-volatile element

Patent metadata

Field	Value
Publication number	US-9601198-B2
Application number	US-201414543487-A
Country	US
Kind code	B2
Filing date	Nov 17, 2014
Priority date	May 18, 2012
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

A memory circuit includes: a bistable circuit ( 30 ) that stores data; nonvolatile elements (MTJ 1 , MTJ 2 ) that store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and a control unit that stores data written in the bistable circuit in a nonvolatile manner and cuts off a power supply to the bistable circuit when the period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and does not store data written in the bistable circuit in a nonvolatile manner and makes the supply voltage for the bistable circuit lower than a voltage during the period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period.

First claim

The invention claimed is:

1. A memory circuit comprising:
a bistable circuit configured to write data;
a nonvolatile element configured to store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and
a control unit configured to store data written in the bistable circuit into the nonvolatile element in a nonvolatile manner and cut off a power supply to the bistable circuit when it is determined that a period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and store no data written in the bistable circuit into the nonvolatile element in a nonvolatile manner and make a supply voltage for the bistable circuit lower than a voltage during a period to read data from or write data into the bistable circuit when it is determined that the period not to read or write data is shorter than the predetermined time period.

2. The memory circuit according to claim 1 , wherein
the control unit determines whether the period not to read data from or write data into the bistable circuit is longer than the predetermined time period,
when determining that the period not to read data from or write data into the bistable circuit is longer than the predetermined time period, the control unit stores data written in the bistable circuit into the nonvolatile element in a nonvolatile manner, and cuts off the power supply to the bistable circuit, and
when determining that the period not to read or write data is shorter than the predetermined time period, the control unit does not store data written in the bistable circuit into the nonvolatile element in a nonvolatile manner, and makes the supply voltage for the bistable circuit lower than the voltage during the period to read data from or write data into the bistable circuit.

3. The memory circuit according to claim 1 , wherein the nonvolatile element has one end connected to a node in the bistable circuit, and has the other end connected to a control line.

4. The memory circuit according to claim 3 , wherein the nonvolatile element stores data written in the bistable circuit in a nonvolatile manner by using a current flowing between the one end and the other end.

5. The memory circuit according to any one of claim 3 , wherein the predetermined time period is equal to or longer than (E store SC +E restore SC /((I LS NV −I L SD )×V sleep ),
E store SC representing an energy calculated by subtracting an energy in a case where the supply voltage for the bistable circuit is lowered during a period to store data into the nonvolatile element, from an energy for storing data into the nonvolatile element,
E restore SC representing an energy calculated by subtracting an energy in a case where the supply voltage for the bistable circuit is lowered during a period to restore data from the nonvolatile element, from an energy for restoring data from the nonvolatile element,
I LS NV representing a current consumed in a case where the supply voltage for the bistable circuit is lowered,
I L SD representing a current consumed in a case where the power supply to the bistable circuit is cut off,
V sleep representing a supply voltage in a case where the supply voltage for the bistable circuit is lowered.

6. The memory circuit according to claim 1 , further comprising:
a MOSFET having a source and a drain connected in series to the nonvolatile element between the node and the control line; and
a control unit configured to make a voltage of the control line during a period for the bistable circuit to store data higher than the lowest voltage to be applied to the control line during a period to store data written in the bistable circuit into the nonvolatile element in a nonvolatile manner.

7. The memory circuit according to claim 6 , wherein the control unit makes the voltage of the control line during the period for the bistable circuit to store data higher than a voltage of the control line during a period to cut off the power supply to the bistable circuit.

8. The memory circuit according to claim 1 , wherein the nonvolatile element is a ferromagnetic tunnel junction element.

9. A memory circuit comprising:
a bistable circuit configured to write data;
a nonvolatile element configured to store data written in the bistable circuit in a nonvolatile manner, and restore data stored in a nonvolatile manner into the bistable circuit; and
a control unit configured to store data written in the bistable circuit into the nonvolatile element in a nonvolatile manner and cut off a power supply to the bistable circuit when a period not to read data from or write data into the bistable circuit is longer than a predetermined time period, and store no data written in the bistable circuit into the nonvolatile element in a nonvolatile manner and make a supply voltage for the bistable circuit lower than a voltage during a period to read data from or write data into the bistable circuit when the period not to read or write data is shorter than the predetermined time period,
wherein the predetermined time period is equal to or longer than a period during which an amount of energy consumed when the supply voltage for the bistable circuit during the predetermined time period is lowered becomes equal to an amount of energy consumed when data is stored and restored into the nonvolatile element.

10. The memory circuit according to claim 9 ,
wherein the predetermined time period is equal to or longer than (E store SC +E restore SC /((I LS NV −I L SD )×V sleep ),
E store SC representing an energy calculated by subtracting an energy in a case where the supply voltage for the bistable circuit is lowered during a period to store data into the nonvolatile element, from an energy for storing data into the nonvolatile element,
E restore SC representing an energy calculated by subtracting an energy in a case where the supply voltage for the bistable circuit is lowered during a period to restore data from the nonvolatile element, from an energy for restoring data from the nonvolatile element,
I LS NV representing a current consumed in a case where the supply voltage for the bistable circuit is lowered,
I L SD representing a current consumed in a case where the power supply to the bistable circuit is cut off,
V sleep representing a supply voltage in a case where the supply voltage for the bistable circuit is lowered.

11. A memory circuit comprising:
a bistable circuit configured to write data;
a nonvolatile element configured to store data written in the bistable circuit in a nonvolatile manner and restore data stored in a nonvolatile manner into the bistable circuit by changing a resistance value with a current flowing between one end and the other end, the nonvolatile element having the one end connected to a node in the bistable circuit and the other end connected to a control line;
an FET having a source and a drain connected in series to the nonvolatile element between the node and the control line; and
a control unit configured to make a highest voltage to be applied to a gate of the FET during a period to restore data stored in the nonvolatile element in a nonvolatile manner into the bistable circuit lower than a voltage of a node being at a high level in the bistable circuit during a period to write data into and read data from the bistable circuit in a volatile manner.

12. The memory circuit according to claim 11 , wherein the control unit makes a highest voltage to be applied to the gate during a period to store data written in the bistable circuit into the nonvolatile element in a nonvolatile m

Assignees

• Japan Science & Tech Agency

Inventors

• SHUTO Yusuke
• Yamamoto Shuichiro
• Sugahara Satoshi

Classifications

• G11C14/0081 Primary

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C14/00

  Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down · CPC title

• G11C11/412

  using field-effect transistors only · CPC title