Cross point memory control

Patent metadata

Field	Value
Publication number	US-9601193-B1
Application number	US-201514853246-A
Country	US
Kind code	B1
Filing date	Sep 14, 2015
Priority date	Sep 14, 2015
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

First claim

What is claimed is:

1. An apparatus comprising:
a memory controller comprising a word line (WL) control module, a bit line (BL) control module and a control information store for storing control information, wherein the control information store coupled to the word line control module and the bit line control module, the memory controller to determine a WL address based, at least in part, on a received memory address, the memory controller further to determine a BL address; and
a parameter selection module to select a value of a control parameter based, at least in part, on the WL address, the BL address, or a combination thereof.

2. The apparatus of claim 1 , wherein the control parameter is related to selecting a memory access operation on a target memory cell, performing a memory access operation on a target memory cell, or a combination thereof.

3. The apparatus of claim 1 , wherein the control parameter is selected from a group comprising a source voltage, a source current amplitude, a selection time interval duration, a sensing time interval duration and a source pulse duration.

4. The apparatus of claim 1 , wherein the selected value is associated with a range of WL addresses, a range of BL addresses, or a combination thereof.

5. The apparatus of claim 1 , wherein the control information store stores control information comprising at least one value for each of a first plurality of control parameters and at least one of associated region information, an associated WL address range, an associated BL address range, or a combination thereof.

6. The apparatus of claim 1 , wherein the WL control module, the BL control module, or a combination thereof comprises a control parameter store to store at least one value for each of a second plurality of control parameters.

7. A method comprising:
determining, by a memory controller, a word line (WL) address based, at least in part, on a received memory address;
determining, by the memory controller, a bit line (BL) address;
storing, by a control information store, control information, wherein the control information store coupled to a word line control module and a bit line control module; and
selecting, by a parameter selection module, a value of a control parameter based, at least in part, on the WL address, the BL address, or a combination thereof.

8. The method of claim 7 , wherein the control parameter is related to selecting a memory access operation on a target memory cell, performing a memory access operation on a target memory cell, or a combination thereof.

9. The method of claim 7 , wherein the control parameter is selected from a group comprising a source voltage, a source current amplitude, a selection time interval duration, a sensing time interval duration and a source pulse duration.

10. The method of claim 7 , wherein the selected value is associated with a range of WL addresses, a range of BL addresses, or a combination thereof.

11. The method of claim 7 , wherein the control information comprises at least one value for each of a first plurality of control parameters and associated region information, an associated WL address range, an associated BL address range, or a combination thereof.

12. The method of claim 7 , further comprising:
storing, by a WL control module, a BL control module, or a combination thereof, at least one value for each of a second plurality of control parameters to a control parameter store.

13. A system comprising:
a processor;
a cross-point memory array comprising a memory cell, a word line (WL) and a bit line (BL), the memory cell coupled between the word line and the bit line; and
a memory controller comprising:
a word line (WL) control module;
a bit line (BL) control module;
a control information store for storing control information, wherein the control information store coupled to the word line control module and the bit line control module; and
a parameter selection module,
the memory controller to determine a WL address based, at least in part, on a received memory address, the memory controller further to determine a BL address,
the parameter selection module to select a value of a control parameter based, at least in part, on the WL address, the BL address, or a combination thereof.

14. The system of claim 13 , wherein the control parameter is related to selecting a memory access operation on a target memory cell, performing a memory access operation on a target memory cell, or a combination thereof.

15. The system of claim 13 , wherein the control parameter is selected from a group comprising a source voltage, a source current amplitude, a selection time interval duration, a sensing time interval duration and a source pulse duration.

16. The system of claim 13 , wherein the selected value is associated with a range of WL addresses, a range of BL addresses, or a combination thereof.

17. The system of claim 13 , wherein the control information store stores control information comprising at least one value for each of a first plurality of control parameters and associated region information, an associated WL address range, an associated BL address range, or a combination thereof.

18. The system of claim 13 , wherein at least one of the WL control module, the BL control module, or a combination thereof comprises a control parameter store to store at least one value for each of a second plurality of control parameters.

19. The system of claim 13 , further comprising at least one of a network interface communicatively coupled to the processor and a display communicatively coupled to the processor.

Assignees

• Intel Corp

Inventors

• Zeng Raymond W
• Taub Mase J
• Pangal Kiran
• Guliani Sandeep K

Classifications

• G11C8/06

  Address interface arrangements, e.g. address buffers · CPC title

• G11C2013/0052

  Read process characterized by the shape, e.g. form, length, amplitude of the read pulse · CPC title

• G11C13/0028 Primary

  Word-line or row circuits · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title