Drive device and display device

Patent metadata

Field	Value
Publication number	US-9601074-B2
Application number	US-201615159924-A
Country	US
Kind code	B2
Filing date	May 20, 2016
Priority date	Feb 20, 2012
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Included are: refresh a rate changing section ( 15 ) for changing a refresh rate of a display panel ( 2 ) by configuring settings for scan periods during each of which a plurality of gate signal lines (G) of the display panel ( 2 ) are sequentially scanned and for pause periods during each of which sequential scanning of the plurality of gate signal lines (G) is suspended; and a drive amount control section ( 20 ) for controlling, in accordance with a ratio of the scan periods to the pause periods, drive time during which each of the gate signal lines is driven in each of the scan periods.

First claim

The invention claimed is:

1. A drive device for driving a display panel having a plurality of pixels, comprising:
a timing controller that:
changes a refresh rate of the display panel by configuring settings for scan periods during each of which a plurality of gate signal lines of the display panel are sequentially scanned and for pause periods during each of which sequential scanning of the plurality of gate signal lines is suspended; and
controls, in accordance with a ratio of the scan periods to the pause periods, a pulse width of a drive pulse on each of the gate signal lines and a drive time during which each of the gate signal lines is driven in each of the scan periods.

2. The drive device as set forth in claim 1 , wherein for each of the plurality of gate signal lines, the timing controller controls the drive time during which the gate signal line is driven that a ratio of the drive time of the gate signal line to non-drive time other than the drive time of the gate signal line is kept constant both prior to and subsequent to a change of the refresh rate.

3. The drive device as set forth in claim 1 , wherein for each of the plurality of gate signal lines, the timing controller controls the drive time of the gate signal line such that the drive time increases as the ratio of the scan periods to the pause periods decreases.

4. The drive device as set forth in claim 1 , wherein a pulse waveform of a vertical synchronization signal is generated every frame period; and
the scan periods each include one or more frame periods and the pause periods each include one or more frame periods.

5. A display device comprising:
a display panel having a plurality of pixels; and
a drive device as set forth in claim 1 .

6. The display device as set forth in claim 5 , wherein each of the plurality of pixels has a switching element whose semiconductor layer is made of an oxide semiconductor.

7. The display device as set forth in claim 6 , wherein the oxide semiconductor is an oxide composed of indium (In), gallium (Ga), and zinc (Zn).

Assignees

• Sharp Kk

Inventors

• Fujioka Akizumi
• Yanagi Toshihiro
• Ihida Satoshi
• Takahashi Kazuki
• Nakano Taketoshi

Classifications

• G09G2310/062

  Waveforms for resetting a plurality of scan lines at a time · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/067

  Special waveforms for scanning, where no circuit details of the gate driver are given · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title