Local error detection and global error correction

Patent metadata

Field	Value
Publication number	US-9600359-B2
Application number	US-201214396327-A
Country	US
Kind code	B2
Filing date	May 31, 2012
Priority date	May 31, 2012
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An example system in accordance with an aspect of the present disclosure is to use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED is to be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC information, in response to identifying the error.

First claim

What is claimed is:

1. A method, comprising:
computing local error detection (LED) information per cache line segment of data associated with a rank of a memory, based on an error detection code;
generating a global error correction (GEC) information for the cache line segment based on an error correction code;
checking data fidelity in response to each memory read operation, based on the LED information, to identify a presence of an error and an error location, at a given cache line segment, of the error among cache line segments of the rank, along with locations of error-free segments; and
correcting the cache line segment having the error based on the GEC information, in response to identifying the error, using the error location to apply correction to the cache line segment having the error, and reconstructing data corresponding to the error using the locations of error-free segments as identified by the LED information for the segments.

2. The method of claim 1 , further comprising coalescing a plurality of GEC updates, associated with adjacent cache lines, to be sent together.

3. The method of claim 1 , wherein the error detection code is to identify the presence of an error and the location of the error within a cache line segment of the rank.

4. The method of claim 1 , further comprising storing the LED information and the GEC information computed for the cache line segment of data at the cache line segment associated with the data.

5. The method of claim 1 , further comprising storing the LED information and the GEC information computed for the cache line segment of data in a memory row different from a memory row associated with the data.

6. A method, comprising:
performing a local error detection (LED) in response to each memory read operation, based on an error detection code computed over a cache line segment, to detect an error location, at a given cache line segment, of an error at a chip-granularity among N data chips in a rank, along with locations of error-free segments;
performing a global error correction (GEC) over the cache line segment on the N data chips in the rank in response to detecting the error, the GEC based on an error correction code to generate GEC information; and
reconstructing data segments having the error by using the error location at the given cache line segment among the cache line segments to apply correction to the cache line segment having the error, and reconstructing data corresponding to the error, based on the locations of error-free segments as identified by the LED information for those segments, and the GEC information for those segments.

7. The method of claim 6 , wherein a plurality of GEC updates to adjacent cache lines are coalesced and sent together.

8. The method of claim 6 , wherein the error correction code is based on N cache line segments.

9. The method of claim 6 , further comprising updating the GEC information in response to a write operation.

10. The method of claim 6 , further comprising storing the GEC information in a row buffer of corresponding cache line, in a reserved region in each of the N data chips.

11. The method of claim 6 , further comprising storing data and corresponding LED information on each chip of the rank, based on a physical data mapping policy; and providing the data and LED information in response to a cache line access request.

12. The method of claim 6 , further comprising generating a tiered error correction code to protect the GEC information, wherein the tiered error correction code is stored on an N th chip and is to be used to recover the GEC information based on GEC information segments from a plurality of chips.

13. The method of claim 12 , further comprising identifying an uncorrectable double-chip failure, based on detecting, during a GEC phase, an error in the GEC row of interest based on the tiered error correction code.

14. A memory controller to:
verify data fidelity, in response to each memory read operation, based on local error detection (LED) information for a cache line segment of data associated with a rank of a memory;
identify a presence and an error location, at a given cache line segment, of an error among cache line segments of the rank according to the LED information, along with locations of error-free segments;
generate a global error correction (GEC) information for the cache line segment based on an error correction code; and
correct the cache line segment having the error based on the GEC information, in response to identifying the error, using the error location at the given cache line segment among the cache line segments to apply correction to the cache line segment having the error, and reconstructing data corresponding to the error using the locations of error-free segments as identified by the LED information for those segments.

15. The memory controller of claim 14 , wherein the LED and GEC information is mapped according to firmware information associated with the memory controller.

Assignees

• Udipi Aniruddha Nagendran
• Muralimanohar Naveen
• Jouppi Norman Paul
• Davis Alan Lynn
• Balasubramonian Rajeev
• Hewlett Packard Entpr Dev Lp

Inventors

• Udipi Aniruddha Nagendran
• Muralimanohar Naveen
• Jouppi Norman Paul
• Davis Alan Lynn
• Balasubramonian Rajeev

Classifications

• G06F11/108

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G06F11/1064 Primary

  in cache or content addressable memories · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• G11C2029/0409

  Online test · CPC title