Integrated circuit with a patching function

Patent metadata

Field	Value
Publication number	US-9600207-B2
Application number	US-201314050449-A
Country	US
Kind code	B2
Filing date	Oct 10, 2013
Priority date	Mar 15, 2013
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An integrated circuit with a patching function comprises a one-time programmable memory (OTP), a random access memory (RAM), and a control unit. The control unit copies data stored on the OTP into the RAM to obtain a copied image mirroring said data. It checks for presence of one or more patch instructions in the OTP, and, if a patch instruction is found in the OTP, modifies a portion of the copied image based on the patch instruction, to obtain a patched image stored in the RAM. The integrated circuit further comprises a processing unit configured to access the patched image in the RAM. The patch can be provided wirelessly.

First claim

What is claimed is:

1. An integrated circuit with a patching function, the integrated circuit comprising:
a one-time programmable memory (OTP);
a random access memory (RAM);
a control unit arranged for:
copying data stored in a predetermined first address range of the OTP into the RAM to obtain a copied image mirroring said data;
checking for presence of a patch instruction in a predetermined second address range of the OTP, wherein the predetermined first address range is different from the predetermined second address range, wherein the patch instruction specifies a change to be made to the data, and if a patch instruction is found in the predetermined second address range of the OTP, modifying a portion of the copied image based on the patch instruction, to obtain a patched image stored in the RAM,
wherein the OTP has memory addresses in an OTP address range covering addresses from a lowest OTP address to a highest OTP address, and wherein the predetermined first address range is located at one end of the OTP address range, and wherein the predetermined second address range is located at or near the other end of the OTP address range.

2. The integrated circuit of claim 1 , further comprising a processing unit configured to access the patched image in the RAM.

3. The integrated circuit of claim 1 , wherein the data stored on the OTP comprises an executable program code, and wherein the patch instruction comprises a software patch to update the executable program code so as to obtain updated program code.

4. The integrated circuit of claim 3 , further comprising a processing unit arranged for executing the updated executable program code stored in the patched image in the RAM.

5. The integrated circuit of claim 1 , comprising a communication unit for receiving an external signal representing a patch of the data stored on the OTP; and wherein the control unit is arranged for storing subsequently received patches onto contiguous memory locations of the OTP.

6. The integrated circuit of claim 1 , wherein the patch instruction comprises a patch address and a patch data block, wherein the patch address is indicative of an address within the copied image, and wherein the control unit is arranged for overwriting a portion of the copied image with the patch data block, based on the address.

7. The integrated circuit of claim 1 , wherein the patch instruction comprises a patch address, an indication of a word size, and a word value in accordance with the word size, wherein the patch address is indicative of an address within the copied image, and wherein the control unit is arranged for overwriting a word of the copied image with the word value based on the patch address, wherein the word of the copied image has a size corresponding to the word size of the patch instruction.

8. A one-time programmable memory (OTP) comprising:
data comprising an application code or an application data; and
at least one patch instruction stored in a predetermined second address range outside an predetermined first address range of the OTP comprising the data, wherein the patch instruction comprises a patch address and a patch data block, wherein the patch address is indicative of an address within the address range of the OTP comprising the data, and wherein the patch data block is indicative of data that replaces a portion of the data comprising the application code or the application data, based on the patch address,
wherein the OTP has memory addresses in an OTP address range covering addresses from a lowest QTP address to a highest OTP address, and wherein the predetermined first address range is located at one end of the OTP address range, and wherein the predetermined second address range is located at or near the other end of the OTP address range.

9. A method of patching an OTP, comprising the steps of:
providing a one-time programmable memory (OTP), a random access memory (RAM), and a processing unit;
copying data stored in a predetermined first address range of the OTP into the RAM to obtain a copied image mirroring said data;
checking for presence of a patch instruction in a predetermined second address range of the OTP, wherein the predetermined first address range is different from the predetermined second address range, wherein the patch instruction specifies a change to be made to the data, and if a patch instruction is found in the predetermined second address range of the OTP, modifying a portion of the copied image based on the patch instruction, to obtain a patched image stored in the RAM,
wherein the OTP has memory addresses in an OTP address range covering addresses from a lowest OTP address to a highest OTP address, and wherein the predetermined first address range is located at one end of the OTP address range, and wherein the predetermined second address range is located at the other end of the OTP address range.

10. The method of claim 9 , wherein a computer program product comprises instructions for causing a processing unit to perform the method of claim 9 .

11. The method of claim 9 , wherein the data stored on the OTP comprise an executable program code.

12. The method of claim 11 , wherein the processing unit may be arranged for executing the updated executable program code stored in the patched image in the RAM.

13. The method of claim 9 , wherein the patch instruction comprises a patch address, an indication of a word size, and a word value in accordance with the word size wherein the patch address is indicative of an address within the copied image, and the control unit is arranged for overwriting a word of the copied image with the word value based on the patch address, wherein the word of the copied image has a size corresponding to the word size of the patch instruction.

14. A method of patching an OTP, comprising the steps of:
(1) providing a system comprising a one-time programmable memory (OTP), a random access memory (RAM), and a processing unit;
(2) start patching;
(3) copying data stored in the RAM;
(4) initializing a OTP variable header (HDR) to a highest memory address or to a predetermined value where the first patch would be stored;
(5) read the OTP address HDR;
(6) checking if each of 0th to 15th bits of this OTP HDR address equals zero and, if it is so, then end patching method, else go to step 7;
(7) applying the patch;
(8) checking if the 15th bit of the OTP HDR address, which is a patch type indicator bit, is zero and, if it is so, then a length of the block is extracted from bits 16 to 31 of the OTP HDR address and go to step (9), else go to step 11;
(9) extracting destination address from bits 0 to 14 of the OTP HDR address and a block having such a length is copied to the designated address;
(10) decreasing variable OTP HDR address by the length of the block extracted in step (8) and go to step (5);
(11) extracting length of the block from bits 0 to 11 of the OTP HDR address and align value from bits 12 to 13 of the OTP HDR address;
(12) checking if align value is 1 and, if it is so, then an 8 bit alignment has to be performed, else, if align value is 2, then a 16 bit alignment is to be performed, else, if align value is 3, then a 32 bits alignment is to be performed, wherein in the alignment steps a target address and data to be copied are determined;
(13) copying the data to the address determined in step (12);
(14) checking if all patches of the patch instruction have been processed and, if it is so, then go to step (10), else go to step (12) to process a next patch.

15. The method of claim 14 , wherein the process start is triggered by a power-u

Assignees

• Dialog Semiconductor Bv

Inventors

• Moschopoulos Nikolaos
• Chanos Dimitris
• Sifnaios Ioannis
• Ninos Konstantinos
• Papadopoulos Dimitrios

Classifications

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F9/328

  for runtime instruction patching · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F8/66 Primary

  of program code stored in read-only memory [ROM] · CPC title