Enhancing power-performance efficiency in a computer system when bursts of activity occurs when operating in low power

Patent metadata

Field	Value
Publication number	US-9600058-B2
Application number	US-201414313597-A
Country	US
Kind code	B2
Filing date	Jun 24, 2014
Priority date	Jun 24, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a plurality of processing cores,
a plurality of graphics cores,
a power management unit to,
accumulate a budget while the plurality of processing cores are in a low processor utilization state,
detect an occurrence of a burst of high activity within the low processor utilization period,
check whether a level of the burst of high activity is above a first threshold value and the budget is above a second threshold value, and
increase a frequency of a clock signal provided to the plurality of processing cores to a peak value of frequency if the level of the burst of high activity is above the first threshold value and the budget is above the second threshold value.

2. The integrated circuit of claim 1 wherein the power management unit to detect an occurrence of the burst of high activity based on one or more processor activity signals.

3. The integrated circuit of claim 1 , wherein the budget represents an amount of idleness of the plurality of processing cores in one or more previous time windows, which occur prior to occurrence of the burst of high activity.

4. The integrated circuit of claim 3 , wherein the budget to accumulate if the amount of idleness of the plurality of processing cores is high and the budget to decrease in response to occurrence of an activity.

5. The integrated circuit of claim 1 , wherein the second threshold value is equal to a high percentage of a maximum budget that can be accumulated to ensure that there is sufficient budget to process the burst of high activity at a peak frequency.

6. The integrated circuit of claim 1 , wherein the first threshold value is equal to a high percentage of an allowable maximum levels of an activity.

7. The integrated circuit of claim 1 , wherein the peak value of frequency includes turbo frequency.

8. The integrated circuit of claim 1 wherein the power management unit is operable to control one or phase locked-loop circuits to increase the frequency of clock signals provided to the plurality of processing cores.

9. A method in an integrated circuit, comprising:
accumulating a budget while a plurality of processing cores are in a low processor utilization state,
detecting an occurrence of a burst of high activity within the low processor utilization period,
checking whether a level of the burst of high activity is above a first threshold value and the budget is above a second threshold value, and
increasing a frequency of a clock signal provided to the plurality of processing cores to a peak value of frequency if the level of the burst of high activity is above the first threshold value and the budget is above the second threshold value.

10. The method of claim 9 , wherein detecting an occurrence of the burst of high activity is based on one or more processor activity signals.

11. The method of claim 9 , wherein the budget represents an amount of idleness of the plurality of processing cores in one or more previous time windows, which occur prior to occurrence of the burst of high activity.

12. The method of claim 11 , wherein the budget to accumulate if the amount of idleness of the plurality of processing cores is high and the budget to decrease in response to occurrence of an activity.

13. The method of claim 9 , wherein the second threshold value is equal to a high percentage of a maximum budget that can be accumulated to ensure that there is sufficient budget to process the burst of high activity at a peak frequency.

14. The method of claim 9 , wherein the first threshold value is equal to a substantially high percentage of an allowable maximum levels of an activity.

15. The method of claim 9 , wherein the peak value of frequency includes turbo frequency.

16. The method of claim 9 further comprises controlling one or more phase locked-loop circuits to increase the frequency of clock signals provided to the plurality of processing cores.

17. A computing system, comprising:
a memory,
a chipset,
a plurality of input-output devices,
a network interface,
a processor, the processor further comprises a plurality of processing cores, a plurality of graphics cores, and a power management unit, wherein the processor to,
accumulate a budget while the plurality of processing cores are in a low processor utilization state,
detect an occurrence of a burst of high activity within the low processor utilization period,
check whether a level of the burst of high activity is above a first threshold value and the budget is above a second threshold value, and
increase a frequency of a clock signal provided to the plurality of processing cores to a peak value of frequency if the level of the burst of high activity is above the first threshold value and the budget is above the second threshold value.

18. The computing system of claim 17 wherein the power management unit is operable to detect an occurrence of the burst of high activity based on one or more processor activity signals.

19. The computing system of claim 17 , wherein the budget represents an amount of idleness of the plurality of processing cores in one or more previous time windows, which occur prior to occurrence of the burst of high activity.

20. The computing system of claim 19 , wherein the budget to accumulate if the amount of idleness of the plurality of processing cores is high and the budget to decrease in response to occurrence of an activity.

21. The computing system of claim 17 , wherein the second threshold value is equal to a high percentage of a maximum budget that can be accumulated to ensure that there is sufficient budget to process the burst of high activity at a peak frequency.

22. The computing system of claim 17 , wherein the first threshold value is equal to a high percentage of an allowable maximum levels of an activity.

23. The computing system of claim 17 , wherein the peak value of frequency includes turbo frequency.

24. The computing system of claim 17 wherein the processor is operable to control one or phase locked-loop circuits to increase the frequency of clock signals provided to the plurality of processing cores.

Assignees

• Abu Salah Hisham
• Weissmann Eliezer
• Rotem Efraim
• Diefenbaugh Paul S
• Schwartz Jay D
• Tripathi Sharad C
• Intel Corp

Inventors

• Abu Salah Hisham
• Weissmann Eliezer
• Rotem Efraim
• Diefenbaugh Paul S
• Schwartz Jay D
• Tripathi Sharad C

Classifications

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title