Methods and apparatus for an ISFET

Patent metadata

Field	Value
Publication number	US-9599587-B2
Application number	US-201414478149-A
Country	US
Kind code	B2
Filing date	Sep 5, 2014
Priority date	Jun 4, 2010
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

First claim

What is claimed is:

1. A method of forming a CMOS ISFET, comprising:
providing a substrate;
forming a floating gate structure over the substrate, wherein the floating gate structure includes a metal plate configured to sense an ion concentration of a fluid adjacent to the metal plate; and
forming a control gate structure communicatively coupled to the floating gate structure, such that the control gate structure is configured to receive a bias voltage and effect transfer of charge selectively between the floating gate structure and the control gate structure;
wherein the at least one control gate structure includes a control gate electrode coupled to the substrate via a conductive interconnect, and a capacitor structure formed by the substrate, the floating gate structure, and an oxide layer provided therebetween.

2. The method of claim 1 , wherein the capacitor structure is formed between the floating gate and a well provided within the substrate.

3. The method of claim 1 , wherein the control gate structure includes two control gates, each forming a respective capacitor with the substrate.

4. The method of claim 1 , further including forming at least one metal-insulator-metal capacitor coupled between the floating gate structure and a first conductive structure.

5. The method of claim 1 , wherein forming the floating gate structure includes forming a polysilicon structure.

6. The method of claim 2 , wherein the well comprises an n-type impurity diffusion region.

7. A method of forming an ISFET, comprising:
providing a substrate;
forming, within the substrate, a source region and a drain region having a channel region therebetween;
forming a gate dielectric layer over the channel region;
forming a floating gate structure on the gate dielectric over the channel region, the floating gate structure being electrically coupled to a first conductive structure and configured to electrically communicate with a fluid having an ion concentration; and
forming at least one control gate structure at least partially in the substrate and electrically coupled to the floating gate structure, the control gate structure configured to accept a voltage bias and to cause the movement of charge between the floating gate structure and the control gate structure in response to the voltage bias, wherein the at least one control gate structure is formed such that it comprises a control gate electrode coupled to the substrate via a conductive interconnect, and a capacitor structure formed by the substrate, the floating gate, and an oxide layer provided therebetween.

8. The method of claim 7 , wherein the capacitor structure is formed between the floating gate and a well provided within the substrate.

9. The method of claim 7 , wherein the at least one control gate structure is formed such that it includes two control gates, each coupled to a respective capacitor structure formed by the substrate, the floating gate, and an oxide layer provided therebetween.

10. The method of claim 7 , further including forming at least one metal-insulator-metal capacitor coupled between the floating gate structure and the first conductive structure.

11. The method of claim 7 , wherein the floating gate structure is formed such that it comprises polysilicon.

Assignees

• Parris Patrice M
• Chen Weize
• De Souza Richard J
• Hoque Md M
• Mckenna John M
• Nxp Usa Inc

Inventors

• Parris Patrice M
• Chen Weize
• De Souza Richard J
• Hoque Md M
• Mckenna John M

Classifications

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H01L27/11526

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• G11C16/0416

  comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM · CPC title