Random spread spectrum modulation

Patent metadata

Field	Value
Publication number	US-9596038-B2
Application number	US-201213422605-A
Country	US
Kind code	B2
Filing date	Mar 16, 2012
Priority date	Mar 16, 2012
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

Representative implementations of devices and techniques provide a spread spectrum clocking signal. In a frequency synthesizer, a sequence of values may be generated and used to modulate a frequency of an input signal to the frequency synthesizer.

First claim

What is claimed is:

1. An electrical circuit comprising:
a digitally controlled oscillator (DCO) arranged to generate a clocking signal; and
a random number generator arranged to generate a sequence of random values, the sequence of random values arranged to modulate a frequency of the clocking signal to form a spread spectrum clocking signal;
a digital loop filter, wherein the sequence of random values is injected into a signal path of the electrical circuit prior to the digital loop filter; and
a second random number generator arranged to generate a second sequence of values, the second sequence of values arranged to modulate the frequency of the clocking signal to form the spread spectrum clocking signal, the second random number generator being upstream from the digital loop filter.

2. The electrical circuit of claim 1 , wherein the second sequence of values comprises random or pseudo-random values.

3. The electrical circuit of claim 1 , wherein the second random number generator comprises an analog random generator.

4. The electrical circuit of claim 1 , wherein one of the sequence of random values and the second sequence of values is injected into a signal path of the electrical circuit ahead of the digital loop filter and the other of the sequence of random values and the second sequence of values is injected into the signal path of the electrical circuit after the digital loop filter.

5. The electrical circuit of claim 1 , further comprising a phase-locked loop (PLL) circuit, the PLL circuit including the DCO.

6. The electrical circuit of claim 1 , wherein the sequence of random values is injected into a signal path of the electrical circuit ahead of the DCO.

7. The electrical circuit of claim 1 , wherein the random number generator comprises a pseudo-random binary sequence (PRBS) generator.

8. The electrical circuit of claim 1 , wherein the random number generator comprises a digital or analog chaotic map.

9. The electrical circuit of claim 1 , wherein the random number generator comprises one or more delta-sigma modulators of arbitrary order.

10. The electrical circuit of claim 1 , wherein the random number generator is a fully implemented digital circuit.

11. The electrical circuit of claim 1 , wherein the random number generator comprises logic that enables generation of the sequence of values based on one or more values associated with one or more sequences of values.

12. The electrical circuit of claim 11 , wherein the logic further enables generation of the sequence of values based on one or more attributes related to a system associated with the random number generator.

13. The electrical circuit of claim 1 , wherein the sequence of random values is generated based on attributes associated with the electrical circuit.

14. The electrical circuit of claim 13 , wherein the at least one of the attributes is instantaneous or accumulated jitter caused by the electrical circuit.

15. The electrical circuit of claim 1 , further comprising a loop filter and another random number generator, the another random number generator to generate another sequence of random values for injection in a signal path preceding the loop filter and the random number generator to inject the sequence of random values in another signal path succeeding the loop filter.

16. An apparatus comprising:
a frequency synthesizer arranged to synthesize a clocking signal; and
a plurality of value generators each arranged to generate a sequence of values, each sequence of values arranged to modulate a frequency of the clocking signal to form a spread spectrum clocking signal, wherein a first of the plurality of value generators precedes a loop filter and a second of the plurality of value generators follows the loop filter, wherein each of the plurality of value generators is a separate random or pseudo-random signal generator.

17. The apparatus of claim 16 , wherein the frequency synthesizer is arranged to synthesize the clocking signal based on an input signal, and wherein the input signal is modulated at least at two discrete points along a signal path of the apparatus.

18. The apparatus of claim 16 , wherein the spread spectrum clocking signal is centered about a nominal frequency of the synthesized clocking signal.

19. The apparatus of claim 16 , wherein the frequency synthesizer comprises one of a digital, analog, or mixed signal phase-locked loop (PLL) device.

20. A method comprising:
synthesizing a clocking signal;
generating a sequence of random or pseudo-random values;
generating a second sequence of random or pseudo-random values, the second sequence of random or pseudo-random values not derived from the sequence of random or pseudo-random values;
modulating a frequency of the clocking signal with the sequence of random or pseudo-random values and the second sequence of random or pseudo-random values; and
generating a spread spectrum clock signal based on the modulating.

21. The method of claim 20 , further comprising:
receiving an input signal;
digitally adding the sequence of random or pseudo-random values to the input signal; and
generating the spread spectrum clocking signal based on the input signal, the sequence of random or pseudo-random values, and the second sequence of random or pseudo-random values.

22. The method of claim 20 , further comprising:
receiving an input signal;
digitally adding the second sequence of random or pseudo-random values to the input signal; and
generating the spread spectrum clocking signal based on the input signal, the sequence of random or pseudo-random values, and the second sequence of random or pseudo-random values.

23. The method of claim 20 , further comprising:
tracking the sequence of the random or pseudo-random values in sets of values; and
generating a next set of values based on a phase accumulation effect of a previous set of values.

24. The method of claim 20 , wherein the sequence of random or pseudo-random values comprises a sequence of positive and negative offsets of a nominal frequency of the clocking signal.

25. The method of claim 20 , wherein the sequence of random or pseudo-random values includes sets of values comprising a random value followed by a value of the same magnitude having an opposite polarity.

Assignees

• Da Dalt Nicola
• Pridnig Peter
• Grollitsch Werner
• Infineon Technologies Ag

Inventors

• Da Dalt Nicola
• Pridnig Peter
• Grollitsch Werner

Classifications

• H04B15/04 Primary

  the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder · CPC title

• H04B1/707

  using direct sequence modulation · CPC title