Device for controlling motor driving

Patent metadata

Field	Value
Publication number	US-9595898-B1
Application number	US-201615054784-A
Country	US
Kind code	B1
Filing date	Feb 26, 2016
Priority date	Aug 18, 2015
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

According to one embodiment, a device for controlling motor driving which includes a first comparator, a second comparator, a zero level detecting portion, and a data determining portion is provided. The first comparator compares a voltage induced in a coil with a first threshold value. The second comparator compares the induced voltage with a second threshold value which is different from the first threshold value. The zero level detecting portion detects that a current flowing in an H-bridge circuit is zero. The data determining portion determines a value of digital data to be inputted to a DA convertor which generates a reference voltage for use in controlling a driving current of the motor based on an output of the first comparator, an output of the second comparator and an output of the zero level detecting portion.

First claim

What is claimed is:

1. A device for controlling motor driving which can be used in a system to control a current flowing in an H-bridge circuit connected to a coil of a motor comprising:
a first comparator which compares a voltage induced in the coil with a first threshold value;
a second comparator which compares the induced voltage with a second threshold value which is different from the first threshold value;
a zero level detecting portion which detects that the current flowing in the H-bridge circuit is zero; and
a data determining portion which determines a value of digital data to be inputted to a DA converter that generates a reference voltage for use in controlling a driving current of the motor based on an output of the first comparator, an output of the second comparator and an output of the zero level detecting portion.

2. The device according to claim 1 , wherein,
in the case that an output of the first comparator and an output of the second comparator which are outputted during a period from when the zero level detecting portion detects that the current flowing in the coil is zero until when a clock signal rises are defined as a first output and as a second output respectively,
the data determining portion reduces a value of digital data to be inputted to the DA converter when the first output indicates that the induced voltage exceeds the first threshold value and the second output indicates that the induced voltage exceeds the second threshold value, increases the value of digital data when the first output indicates that the induced voltage does not exceed the first threshold value and the second output indicates that the induced voltage does not exceed the second threshold value, and retains a present value of digital data when the first output indicates that the induced voltage exceeds the first threshold value and the second output indicates that the induced voltage does not exceed the second threshold value.

3. The device according to claim 2 , wherein the zero level detecting portion detects that the current flowing in the H-bridge circuit is zero after the H-bridge circuit enters a current regeneration mode.

4. The device according to claim 2 , wherein the H-bridge circuit is in a high impedance state from when the zero level detecting portion detects that the current is zero until when at least the clock signal rises.

5. The device according to claim 2 , wherein the data determining portion comprises:
a first flip-flop circuit including a first data input terminal, a first clock terminal, a reset terminal, and a first output terminal, the first data input terminal being provided with a predetermined voltage, the first clock terminal receiving the output of the zero level detecting portion, and the reset terminal being provided with a clock signal;
a second flip-flop circuit including a second data input terminal, a second clock terminal, and a second output terminal, the second data input terminal receiving the output of the first comparator, the first clock terminal receiving an output of the first flip-flop circuit;
a third flip-flop circuit including a third data input terminal, a third clock terminal, and a third output terminal, the third data input terminal receiving the output of the second comparator, and the third clock terminal being provided with the output of the first flip-flop circuit;
a judging portion which receives outputs from the second and the third flip-flop circuits; and
a register which receives an output from the judging portion and retains the value of digital data to be inputted to the DA convertor.

6. The device according to claim 5 , wherein the data judging portion further comprises:
a forth flip-flop circuit including a forth data input terminal, a forth clock terminal, and a forth output terminal, the forth data input terminal receiving the output of the first comparator, and the forth clock terminal receiving the output of the first flip-flop circuit; and
a fifth flip-flop circuit including a fifth data input terminal, a fifth clock terminal, and a fifth output terminal, the fifth data input terminal receiving the output of the second comparator, and the fifth clock terminal receiving the output of the first flip-flop circuit,
wherein outputs of the fourth and the fifth flip-flop circuits are provided to the judging portion and the judging portion determines the value of digital data to be provided to the register according to the outputs of the second to the fifth flip-flop circuits.

7. The device according to claim 1 , wherein the zero level detecting portion detects that the current flowing in the H-bridge circuit is zero after the H-bridge circuit enters a current regeneration mode.

8. The device according to claim 1 , wherein the data determining portion retains a present value of digital data when the zero level detecting portion does not detect that the current is zero.

9. The device according to claim 1 , wherein the data determining portion initializes the value of digital data when the zero level detecting portion does not detect that the current is zero.

10. The device according to claim 1 , wherein the H-bridge circuit is in a high impedance state from when the zero level detecting portion detects that the current is zero until when at least a clock signal rises.

11. The device according to claim 1 , wherein the data determining portion comprises:
a first flip-flop circuit including a first data input terminal, a first clock terminal, a reset terminal, and a first output terminal, the first data input terminal being provided with a predetermined voltage, the first clock terminal receiving the output of the zero level detecting portion, and the reset terminal being provided with a clock signal,
a second flip-flop circuit including a second data input terminal, a second clock terminal, and a second output terminal, the second data input terminal receiving the output of the first comparator, the first clock terminal receiving an output of the first flip-flop circuit,
a third flip-flop circuit including a third data input terminal, a third clock terminal, and a third output terminal, the third data input terminal receiving the output of the second comparator, and the third clock terminal being provided with the output of the first flip-flop circuit,
a judging portion which receives outputs from the second and the third flip-flop circuits, and
a register which receives an output from the judging portion and retains the value of digital data to be inputted to the DA convertor.

12. The device according to claim 11 , wherein the data determining portion further comprises:
a forth flip-flop circuit including a forth data input terminal, a forth clock terminal, and a forth output terminal, the forth data input terminal receiving the output of the first comparator, and the forth clock terminal receiving the output of the first flip-flop circuit; and
a fifth flip-flop circuit including a fifth data input terminal, a fifth clock terminal, and a fifth output terminal, the fifth data input terminal receiving the output of the second comparator, and the fifth clock terminal receiving the output of the first flip-flop circuit,
wherein outputs of the fourth and the fifth flip-flop circuits are provided to the judging portion and the judging portion determines the value of digital data to be provided to the register according to the outputs of the second to the fifth flip-flop circuits.

Assignees

• Toshiba Kk

Inventors

• Inoue Kouji
• Asakawa Tooru

Classifications

• H02P6/18 Primary

  without separate position detecting elements · CPC title

• H03K17/6874

  in a symmetrical configuration · CPC title

• H03K5/1536

  Zero-crossing detectors (in measuring circuits G01R19/175) · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K5/24

  the characteristic being amplitude · CPC title