MRAM integration techniques for technology scaling

Patent metadata

Field	Value
Publication number	US-9595662-B2
Application number	US-201615213384-A
Country	US
Kind code	B2
Filing date	Jul 18, 2016
Priority date	Dec 17, 2013
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

First claim

What is claimed is:

1. A method of forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with one or more logic elements, the method comprising:
forming a bottom metal line in a bottom IMD layer;
forming one or more bottom cap layers separating the common IMD layer and the bottom IMD layer;
forming a bottom electrode contact coupled to the bottom metal line;
forming the MTJ on the bottom electrode contact;
forming one or more top cap layers separating the common IMD layer and a top IMD layer; and
forming a top via in the one or more top cap layers, the top via connected to the MTJ, wherein the MTJ is in direct physical contact with the top via such that the MTJ extends between the one or more bottom cap layers and the one or more top cap layers.

2. The method of claim 1 , wherein forming the MTJ comprises forming a bottom electrode on the bottom electrode contact, forming a pinned layer, a barrier layer, and a free layer on top of the bottom electrode, and forming a hard mask.

3. The method of claim 2 , comprising connecting the hard mask to the top via.

4. The method of claim 3 , comprising forming the bottom electrode contact with a first mask and forming the MTJ with a second mask.

5. The method of claim 2 , comprising forming a top electrode on top of the hard mask, and connecting the top electrode to the top via.

6. The method of claim 5 , comprising forming the bottom electrode contact with a first mask and forming the MTJ with a second mask, and forming the top electrode with a third mask.

7. The method of claim 1 , comprising forming the bottom electrode contact in a pattern etched in one of the one or more bottom cap layers.

8. The method of claim 1 , wherein forming the one or more logic elements in the common IMD layer comprises forming a via and a metal line in the common IMD layer, such that a combined height of the via and the metal line matches a combined height of the MTJ and the bottom electrode contact.

9. The method of claim 1 , further comprising forming a protective side cap surrounding the MTJ.

10. A method of forming a magnetoresistive random-access memory (MRAM) device, the method comprising:
patterning a bottom metal line in a bottom IMD layer;
forming one or more bottom cap layers separating bottom IMD layer from a common IMD layer;
patterning a bottom electrode hole in the one or more bottom cap layers for forming a bottom electrode and filling the bottom electrode hole with metal for the bottom electrode;
depositing a magnetic tunnel junction (MTJ) on the bottom electrode;
patterning the MTJ;
depositing dielectric material to form the common IMD layer, and performing planarization on top of the MTJ;
patterning and depositing logic elements in the common IMD layer;
depositing a top cap layer for separating the common IMD layer from a top IMD layer; and
patterning a top via hole in the top cap layer and depositing a top via in the top via hole to connect the MTJ to a top metal line in the top IMD layer, wherein the MTJ is in direct physical contact with the top via, and wherein the MTJ extends between the one or more bottom cap layers and the top cap layer.

11. The method of claim 10 further comprising performing chemical mechanical polishing (CMP) on the bottom electrode prior to depositing the MTJ on the bottom electrode.

12. The method of claim 10 further comprising depositing a side cap layer on the MTJ and patterning the bottom electrode by a mask prior to depositing the top cap layer.

13. The method of claim 10 , wherein the logic elements comprise a via and a common layer metal line.

Assignees

• Qualcomm Inc

Inventors

• Li Xia
• Lu Yu
• Kang Seung Hyuk

Classifications

• H01L43/02 Primary

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/12

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic